Low distortion current switch
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[0020]A system and method are provided for making the load of the clock driver independent of data, thereby reducing third order harmonic distortion. FIG. 3a shows a digital control circuitry with a NAND implementation of an SR latch in accordance with an embodiment of the invention. Such architecture may comprise a data input 310 and a complementary input 315, clock input 320, pre-charging switches 340 and 345, an SR Latch 390, comprising NAND gates 350 and 355, and complementary current outputs 370 and 375, controlled by switches 360 and 365 which may be supplied by current source 380. Switching elements 330 and 335 are coupled to data inputs 310 and 315 accordingly. When turned “ON,” switching elements 330 and 335 provide a path to the SR Latch 390 comprising NAND gates 350 and 355. In one embodiment, switching elements 330 and 335 may be NFETS. The gates of the switching elements 330 and 335 are controlled by clocking signal 320. When the clock is “high,” data from input 310 and...
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