Low distortion current switch

Active Publication Date: 2009-10-29
ANALOG DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In practice, errors and noise occur throughout the system, the effects of which increase with operating frequency.
These effects may be code dependent and may result in harmonic distortion and harmonic spurs in the analog output signal.
Consequently, there may be a signal dependent clocking instant, resulting in third order distortion.
However, the attempt to equalize the loading to the clock by the addition of dummy latches and the corresponding support circuitry, may add to the overall complexity, overhead, mismatch, power consumption, and size of the implementation.

Method used

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  • Low distortion current switch
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Embodiment Construction

[0020]A system and method are provided for making the load of the clock driver independent of data, thereby reducing third order harmonic distortion. FIG. 3a shows a digital control circuitry with a NAND implementation of an SR latch in accordance with an embodiment of the invention. Such architecture may comprise a data input 310 and a complementary input 315, clock input 320, pre-charging switches 340 and 345, an SR Latch 390, comprising NAND gates 350 and 355, and complementary current outputs 370 and 375, controlled by switches 360 and 365 which may be supplied by current source 380. Switching elements 330 and 335 are coupled to data inputs 310 and 315 accordingly. When turned “ON,” switching elements 330 and 335 provide a path to the SR Latch 390 comprising NAND gates 350 and 355. In one embodiment, switching elements 330 and 335 may be NFETS. The gates of the switching elements 330 and 335 are controlled by clocking signal 320. When the clock is “high,” data from input 310 and...

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Abstract

A system and method is provided for code independent switching in a digital-to-analog converter (DAC). A synchronous digital circuit is triggered by a synchronizing clocking signal and develops a digital data signal. A circuit arrangement provides the synchronizing clock a constant load at every clocking cycle, thereby assuring a data independent load. By providing a data independent load to the synchronizing clock at every clocking cycle, third harmonic distortion is advantageously reduced.

Description

COPYRIGHT AND LEGAL NOTICES[0001]A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyrights whatsoever.BACKGROUND INFORMATION[0002]The present invention relates in general to electronic signal processing, and more specifically, to digital to analog signal conversion.[0003]A current steering digital-to-analog converter (DAC) converts a digital data stream input into a corresponding analog signal output. FIG. 1 shows a portion of a typical current steering DAC 100 in which a digital data stream is applied to a synchronous digital output latch 101. “Synchronous” means that the data on the latch input is transferred to the output in response to triggering of the latch by a clocking signal. In some app...

Claims

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Application Information

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IPC IPC(8): H03M1/66H03K19/00
CPCH03K5/135H03K17/162H03K17/04106H03K5/151
InventorSCHOFIELD, WILLIAM GEORGE JOHN
OwnerANALOG DEVICES INC