Intelligent cache replacement mechanism with varying and adaptive temporal residency requirements

Abstract

A method for replacing cached data is disclosed. The method in one aspect associates an importance value to each block of data in the cache. When a new entry needs to be stored in the cache, a cache block for replacing is selected based on the importance values associated with cache blocks. In another aspect, the importance values are set according to the hardware and/or software's knowledge of the memory access patterns. The method in one aspect may also include varying the importance value over time over different processing requirements.

Description

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT[0001]This invention was made with Government support under Contract No.: NBCH020056 (DARPA) awarded by Defense, Advanced Research Projects Agency. The Government has certain rights in this invention.FIELD OF THE INVENTION[0002]The present disclosure generally relates to computer processors and particularly to memory management.BACKGROUND OF THE INVENTION[0003]Cache memory is one of the critical elements in computer processors for achieving good performance on the processors. Generally, a cache is a smaller, faster memory used by a central processing unit of a computer to reduce the average time to access its data or instructions. The cache typically stores copies of the data from the most frequently used main memory locations. The fundamental idea of cache organization is that by keeping the most frequently accessed instructions and data in the fast cache memory, the average memory access time will approach the access t...

AI Technical Summary

Benefits of technology

[0009]In a further aspect, the method may include resetting the value according to a varying expected access pattern for the entry. The setting may be performed by hardware, software or an operation system, or combination thereof. In one aspect, the software and/or the operating system are allowed to read the values from the cache memory control data.

[0010]In another aspect, the method may include maintaining the value assigned to the entry until the entry is replaced. In yet another aspect, the method may include decaying the value. Still in another aspect, the method may include decaying one or more values associated with an associative set of the cache memory when an entry from the associative set is selected for replacement. In another aspect, the method may include periodically decaying one or more values associated with one or more respective entries in the cache.

[0011]Further yet, the method may include decaying one or more values associated with one ...

Problems solved by technology

A cache miss is costly because the data must then be fetched from a higher-level cache, main memory, or potentially another processor's cache on a multiprocessor, which incurs a delay because accessing the other memory is slower than accessing the cache memory.

While LRU performs well in many cases, it may not be suitable for some situations.

A streaming application is an example application where LRU cache replacement may not have the desired performance.

In addition, existing cache solutions ...

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