Semiconductor storage device

Abstract

A voltage of a bit line connected to a memory cell is stepped up to a power supply voltage by a precharge circuit. Before data is read from the memory cell, the voltage of the bit line is stepped down to a voltage level lower than the power supply voltage by a step-down circuit. A precharge switching element controls a connection between a high-potential-side power supply and the precharge circuit and a connection between a low-potential-side power supply and the precharge circuit. A power supply connecting circuit is provided between the precharge switching element and the high-potential-side power supply. A ground connecting circuit is provided between a connecting point at which the precharge switching element is connected to the power supply connecting circuit and the low-potential-side power supply.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a semiconductor storage device comprising a memory cell, a bit line connected to the memory cell, a precharge circuit which steps up a voltage of the bit line up to a power supply voltage, and a step-down circuit which steps down the voltage of the bit line to a voltage level lower than the power supply voltage before data is read from the memory cell.[0003]2. Description of the Related Art[0004]In the field of a semiconductor storage device, there is a conventional technology for improving a data reading speed by stepping down a bit line precharged with a power supply voltage to a voltage level lower than the power supply voltage before data is read so that the power supply voltage level in the bit line can change to a ground level sooner. The change from the power supply voltage level to the ground level in the bit line is detected by a PMO transistor at a subsequent gate. However, whe...

AI Technical Summary

Benefits of technology

[0016]Therefore, a main object of the present invention is to provide a semiconductor storage device capable of reliably preventing the deterioration of a reading speed at the time when data is read from a memory cell by providing a bit line with a step-down circuit without any increase of a load capacity of the bit line, and capable of unfailingly preventing a data-read error by executing a stable step-down control.

[0026]The present invention exerts the following effect. When the precharge circuit is in assert state, the step-down circuit is in negate state. When the step-down circuit is in assert state, the precharge circuit is in negate state. Thus, the precharge circuit and the step-down circuit are in the trade-off relationship in their operation states. In the present invention wherein the relationship is utilized, the precharge circuit is interposed between the step-down circuit and the bit line when the step-down circuit is connected to the bit line. More specifically, the precharge switching element which is turned on at the time of the precharge is provided in the precharge circuit, and one end of the precharge switching element is connected to the bit line, while the other end thereof is connected to the high-potential-side power supply. Then, the power supply connecting circuit is interposed between the precharge switching element and the high-potential-side power supply so that the precharge switching element and the high-potential-side power supply are not constantly connected to each other. Further, the connecting point at which the precharge switching element and the power supply connecting circuit are connected to each other is used as a control node, and the ground connecting circuit is interposed between the control node and the low-potential-side power supply. Accordingly, the control node and the low-potential-side power supply are not constantly connected to each other. The power supply connecting circuit is interposed between the control node and the high-potential-side power supply. The ground connecting circuit is interposed between the control node and the low-potential-side power supply so that the high-potential-side power supply and the low-potential-side power supply will not be electrically short-circuited to each other. The power supply connecting circuit and the ground connecting circuit are turned on and off in the trade-off manner.

[0029]As described, the ground connecting circuit constituting the step-down circuit is connected to the node (control node) of the precharge switching element on the side of the high-potential-side power supply (side of the power supply connecting circuit). The ground connecting circuit is not directly connected to the bit line. The precharge switching element is interposed between the ground connecting circuit and the bit line. Accordingly, a load capacity of the bit line is prevented from increasing. As a result, it becomes possible to shorten the time which requires for carrying out charge and discharge of the bit line at the time of data read. Thereby, the data reading speed improves.

[0030]In the semiconductor storage device thus constituted, the power supply connecting circuit and the ground connecting circuit may be integrally constituted as an inverter which is turned on and off by a common precharge / step-down control signal. Because the precharge / step-down control signal serves as a control signal of the power supply connecting circuit and a control signal of the ground connecting circuit, an area reduction can be improved. Further, there are the following advantages: The on-off control of the power supply connecting circuit and the on-off control of the ground connecting circuit can be performed at the same time, which makes it difficult for through current to flow; and the influence of setup on input signals in the precharge circuit and the step-down circuit can be lessened because the precharge / step-down control signal serves as a control signal of the precharge circuit and a control signal of the step-down circuit.

[0032]According to the present invention, the load capacity of the bit line can be prevented from increasing. Further, the speed at which the data is read from the memory cell can be prevented from deteriorating, and data-read errors can be reliably prevented from happening.

[0033]The technology according to the present invention can control the increase of the load capacity of the bit line and prevent the speed at which the data is read from the memory cell from deteriorating. Therefore, the technology is advantageously applied to a semiconductor storage device such as SRAM for which a higher reading speed is strongly demanded.

Problems solved by technology

However, when a step-down level in the bit line is below an operation region of a transistor for detection, through current and a data-read error may occur.

A similar data-read error also occur in the case where a sense amplifier or a PMOS cross driver is connected to the bit line.

The inflow of too many charges at the time results in the generation of a data-write error.

The static noise margin has been reduced in recent years as the semiconductor is increasingly miniaturized, and the data-write error is more likely to occur.

When the voltage step-down level in the bit line at that time is not enough, the data-write error occurs due to the reason described above.

When the voltage step-down level in the bit line is excessive, an data-write error is caused by charges of “L” level of the bit line which flow into the node at which “H” data of the SRAM is retained.

In the conventional technology, since the step-down transistors QN31 and QN32 of the step-down circuit 15 are directly connected to the bit lines BL and / BL, load capacities of the bit lines BL and / BL are increased, which results in the deterioration of a reading time in a data cycle of reading data from the memory cell.

As a result, the step-down levels of the bit lines BL and / BL also vary, which may result in a data-read error.

Images