Consideration of local routing and pin access during VLSI global routing

Abstract

Global routing and congestion evaluation is enhanced by including consideration of local routing and pin access. Pin information is computed for each global edge based on adjacent tiles, and the wiring track capacity for an edge is reduced based on the pin information. After global routing, the wiring track capacities are increased by previous reduction amounts for detailed routing. The pin information can include pin count for an associated tile, the Steiner tree length for the pins, or relative locations of the pins. Wiring track capacities are preferably reduced by creating blockages in tracks of a particular metal layer of the circuit design used for logic gates of the pins. The blockage tracks can be spread evenly across the wiring tracks of a given edge.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention generally relates to the design and manufacture of integrated circuits, and more particularly to a method of global wire routing for an integrated circuit design.[0003]2. Description of the Related Art[0004]Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements combined to perform a logic function. Cell types include, for example, core cells, scan cells, in...

AI Technical Summary

Benefits of technology

The present invention provides a method for wiring connections in an integrated circuit design using global tiles with limited wiring track capacity. The method involves receiving a description of the circuit design, partitioning it into global tiles, computing pin information for each global edge, reducing the wiring track capacity for that edge based on the pin information, and routing global connections between the tiles using the reduced capacity. The wiring track capacities can be increased for detailed routing of connections between pins. The pin information can include a pin count, a Steiner tree length, or relative pin locations. The method helps improve the overall efficiency of wiring connections in the circuit design.

Problems solved by technology

An IC may include a very large number of cells and require complicated connections between the cells.

Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices, physical design is not practical without the aid of computers.

However, physical synthesis can take days to complete.

A designer can expend considerable effort trying to get the design into a good state in terms of timing and signal integrity, only to subsequently find that it is unroutable.

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