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Modified fin cut after epitaxial growth

a technology of epitaxial growth and fin, applied in the field of micro-drain region and connection of fin field effect transistor, can solve problems such as reducing nfet performan

Inactive Publication Date: 2016-06-16
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The invention is a method and structure for making a semiconductor structure. The method involves forming fins in different regions of a substrate and then adding a gate over the fins. The structure also includes different junctions on the fins in each region and a gate that runs perpendicular to the fins in the intermediate region. The technical effect of this invention is to provide a more complex and efficient semiconductor structure that allows for better performance and reliability.

Problems solved by technology

However, a material that may improve pFinFET performance may reduce nFET performance, and vice versa.

Method used

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  • Modified fin cut after epitaxial growth
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  • Modified fin cut after epitaxial growth

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Embodiment Construction

[0033]Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0034]For purposes of the description hereinafter, terms such as “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. Terms such as “above”, “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first e...

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PUM

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Abstract

A method of forming a gate located above multiple fin regions of a semiconductor device. The method may include removing unwanted fin structures after epitaxially growing junctions.

Description

BACKGROUND[0001]The present invention relates to semiconductor devices, and particularly to forming source / drain regions and connections on fin field effect transistors.[0002]Field effect transistors (FETs) are commonly employed in electronic circuit applications. FETs may include a source region and a drain region spaced apart by a semiconductor channel region. A gate, including a gate dielectric layer, a work function metal layer, and a metal electrode, may be formed above the channel region. By applying voltage to the gate, the conductivity of the channel region may increase and allow current to flow from the source region to the drain region.[0003]Fin field effect transistors (FinFETs) are an emerging technology which may provide solutions to field effect transistor (FET) scaling problems at, and below, the 22 nm node. FinFET structures may include at least a narrow semiconductor fin gated on at least two sides of each of the semiconductor fin, as well as a source region and a d...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L27/12H01L29/161H01L29/16
CPCH01L27/1211H01L29/1608H01L29/161H01L29/16H01L21/3086H01L21/823431H01L21/823821H01L21/845H01L29/66545H01L29/7848
Inventor KANAKASABAPATHY, SIVANANDA K.LIE, FEE LISEO, SOON-CHEONSREENIVASAN, RAGHAVASIMHAN
Owner IBM CORP