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Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor

Active Publication Date: 2017-10-19
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent is about methods and devices that prevent a hazard flush in a processor with multiple slices. The hazard flush is a type of accident that occurs when two instructions, one to load data and another to store it, are scheduled for execution simultaneously. The invention prevents this issue by checking if the store instruction causes a hazard against the load instruction and avoiding the flush of the load reorder queue. This results in faster and more efficient processing.

Problems solved by technology

Since that time, computer systems have evolved into extremely complicated devices.

Method used

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  • Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor

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Embodiment Construction

[0013]Exemplary methods and apparatus for preventing hazard flushes in an instruction sequencing unit of a multi-slice processor in accordance with the present invention are described with reference to the accompanying drawings, beginning with FIG. 1. FIG. 1 sets forth a block diagram of an example system configured for preventing hazard flushes in an instruction sequencing unit of a multi-slice processor according to embodiments of the present invention. The system of FIG. 1 includes an example of automated computing machinery in the form of a computer (152).

[0014]The computer (152) of FIG. 1 includes at least one computer processor (156) or ‘CPU’ as well as random access memory (168) (‘RAM’) which is connected through a high speed memory bus (166) and bus adapter (158) to processor (156) and to other components of the computer (152).

[0015]The example computer processor (156) of FIG. 1 may be implemented as a multi-slice processor. The term ‘multi-slice’ as used in this specificati...

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Abstract

Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor including receiving a load instruction in a load reorder queue, wherein the load instruction is an instruction to load data from a memory location; subsequent to receiving the load instruction, receiving a store instruction in a store reorder queue, wherein the store instruction is an instruction to store data in the memory location; determining that the store instruction causes a hazard against the load instruction; preventing a flush of the load reorder queue based on a state of the load instruction; and re-executing the load instruction.

Description

BACKGROUNDField of the Invention[0001]The field of the invention is data processing, or, more specifically, methods, apparatus, and products for preventing hazard flushes in an instruction sequencing unit of a multi-slice processor.Description of Related Art[0002]The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely complicated devices. Today's computers are much more sophisticated than early systems such as the EDVAC. Computer systems typically include a combination of hardware and software components, application programs, operating systems, processors, buses, memory, input / output devices, and so on. As advances in semiconductor processing and computer architecture push the performance of the computer higher and higher, more sophisticated computer software has evolved to take advantage of the higher performance of the hardware, resulting in computer systems today that ...

Claims

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Application Information

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IPC IPC(8): G06F9/30
CPCG06F9/30043G06F9/3834G06F9/3836G06F9/3861G06F9/3891
Inventor CORDES, ROBERT A.HRUSECKY, DAVID A.MCGLONE, ELIZABETH A.
Owner IBM CORP
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