Transmit fast-path processing on TCP/IP offload network interface device

a network interface device and fast-path processing technology, applied in the field of computer or other network, can solve the problems of increasing the need for such protocol processing, reducing the ability of the cpu to perform other tasks, and avoiding awkward and expensive solutions, so as to avoid unnecessary load on the pci bus, avoid unnecessary load, and quickly move data.

Inactive Publication Date: 2005-11-15
ALACRITECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0049]The CPD 30 collapses multiple protocol stacks each having possible separate states into a single state machine for fast-path processing. As a result, exception conditions may occur that are not provided for in the single state machine, primarily because such conditions occur infrequently and to deal with them on the CPD would provide little or no performance benefit to the host. Such exceptions can be CPD 30 or CPU 28 initiated. An advantage of the invention includes the manner in which unexpected situations that occur on a fast-path CCB are handled. The CPD 30 deals with these rare situations by passing back or flushing to the host protocol stack 44 the CCB and any associated message frames involved, via a control negotiation. The exception condition is then processed in a conventional manner by the host protocol stack 44. At some later time, usually directly after the handling of the exception condition has completed and fast-path processing can resume, the host stack 44 hands the CCB back to the CPD.
[0050]This fallback capability enables the performance-impacting functions of the host protocols to be handled by the CPD network microprocessor, while the exceptions are dealt with by the host stacks, the exceptions being so rare as to negligibly effect overall performance. The custom designed network microprocessor can have independent processors for transmitting and receiving network information, and further processors for assisting and queuing. A preferred microprocessor embodiment includes a pipelined trio of receive, transmit and utility processors. DMA controllers are integrated into the implementation and work in close concert with the network microprocessor to quickly move data between buffers adjacent to the controllers and other locations such as long term storage. Providing buffers logically adjacent to the DMA controllers avoids unnecessary loads on the PCI bus.
[0051]FIG. 3 diagrams the general flow of messages received according to the current invention. A large TCP / IP message such as a file transfer may be received by the host from the network in a number of separate, approximately 64 KB transfers, each of which may be split into many, approximately 1.5 KB frames or packets for transmission over a network. Novell NetWare protocol suites running Sequenced Packet Exchange Protocol (SPX) or NetWare Core Protocol (NCP) over Internetwork Packet Exchange (IPX) work in a similar fashion. Another form of data communication which can be handled by the fast-path is Transaction TCP (hereinafter T / TCP or TTCP), a version of TCP which initiates a connection with an initial transaction request after which a reply containing data may be sent according to the connection, rather than initiating a connection via a several-message initialization dialogue and then transferring data with later messages. In any of the transfers typified by these protocols, each packet conventionally includes a portion of the data being transferred, as well as headers for each of the protocol layers and markers for positioning the packet relative to the rest of the packets of this message.
[0052]When a message packet or frame is received 47 from a network by the CPD, it is first validated by a hardware assist. This includes determining the protocol types of the various layers, verifying relevant checksums, and summarizing 57 these findings into a status word or words. Included in these words is an indication whether or not the frame is a candidate for fast-path data flow. Selection 59 of fast-path candidates is based on whether the host may benefit from this message connection being handled by the CPD, which includes determining whether the packet has header bytes indicating particular protocols, such as TCP / IP or SPX / IPX for example. The small percent of frames that are not fast-path candidates are sent 61 to the host protocol stacks for slow-path protocol processing. Subsequent network microprocessor work with each fast-path candidate determines whether a fast-path connection such as a TCP or SPX CCB is already extant for that candidate, or whether that candidate may be used to set up a new fast-path connection, such as for a TTCP / IP transaction. The validation provided by the CPD provides acceleration whether a frame is processed by the fast-path or a slow-path, as only error free, validated frames are processed by the host CPU even for the slow-path processing.
[0053]All received message frames which have been determined by the CPD hardware assist to be fast-path candidates are examined 53 by the network microprocessor or INIC comparator circuits to determine whether they match a CCB held by the CPD. Upon confirming such a match, the CPD removes lower layer headers and sends 69 the remaining application data from the frame directly into its final destination in the host using direct memory access (DMA) units of the CPD. This operation may occur immediately upon receipt of a message packet, for example when a TCP connection already exists and destination buffers have been negotiated, or it may first be necessary to process an initial header to acquire a new set of final destination addresses for this transfer. In this latter case, the CPD will queue subsequent message packets while waiting for the destination address, and then DMA the queued application data to that destination.
[0054]A fast-path candidate that does not match a CCB may be used to set up a new fast-path connection, by sending 65 the frame to the host for sequential protocol processing. In this case, the host uses this frame to create 51 a CCB, which is then passed to the CPD to control subsequent frames on that connection. The CCB, which is cached 67 in the CPD, includes control and state information pertinent to all protocols that would have been processed had conventional software layer processing been employed. The CCB also contains storage space for per-transfer information used to facilitate moving application-level data contained within subsequent related message packets directly to a host application in a form available for immediate usage. The CPD takes command of connection processing upon receiving a CCB for that connection from the host.

Problems solved by technology

As networks grow increasingly popular and the information communicated thereby becomes increasingly complex and copious, the need for such protocol processing has increased.
It is estimated that a large fraction of the processing power of a host CPU may be devoted to controlling protocol processes, diminishing the ability of that CPU to perform other tasks.
This solution, however, is both awkward and expensive.
But the complexities presented by various networks, protocols, architectures, operating devices and applications generally require extensive processing to afford communication capability between various network hosts.

Method used

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  • Transmit fast-path processing on TCP/IP offload network interface device
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  • Transmit fast-path processing on TCP/IP offload network interface device

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Embodiment Construction

[0046]FIG. 1 shows a host 20 of the present invention connected by a network 25 to a remote host 22. The increase in processing speed achieved by the present invention can be provided with an intelligent network interface card (INIC) that is easily and affordably added to an existing host, or with a communication processing device (CPD) that is integrated into a host, in either case freeing the host CPU from most protocol processing and allowing improvements in other tasks performed by that CPU. The host 20 in a first embodiment contains a CPU 28 and a CPD 30 connected by a PCI bus 33. The CPD 30 includes a microprocessor designed for processing communication data and memory buffers controlled by a direct memory access (DMA) unit. Also connected to the PCI bus 33 is a storage device 35, such as a semiconductor memory or disk drive, along with any related controls.

[0047]Referring additionally to FIG. 2, the host CPU 28 controls a protocol processing stack 44 housed in storage 35, the...

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Abstract

A network interface device provides a fast-path that avoids most host TCP and IP protocol processing for most messages. The host retains a fallback slow-path processing capability. In one embodiment, generation of a response to a TCP / IP packet received onto the network interface device is accelerated by determining the TCP and IP source and destination information from the incoming packet, retrieving an appropriate template header, using a finite state machine to fill in the TCP and IP fields in the template header without sequential TCP and IP protocol processing, combining the filled-in template header with a data payload to form a packet, and then outputting the packet from the network interface device by pushing a pointer to the packet onto a transmit queue. A transmit sequencer retrieves the pointer from the transmit queue and causes the corresponding packet to be output from the network interface device.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit under 35 U.S.C. .sctn.120 of U.S. patent application Ser. No. 09 / 464,283, entitled “INTELLIGENT NETWORK INTERFACE DEVICE AND SYSTEM FOR ACCELERATED COMMUNICATION”, filed Dec. 15, 1999, by Laurence B. Boucher et al., now U.S. Pat. No. 6,427,173 which in turn claims the benefit under 35 U.S.C. .sctn.120 of U.S. patent application Ser. No. 09 / 439,603 entitled “INTELLIGENT NETWORK INTERFACE SYSTEM AND METHOD FOR ACCELERATED PROTOCOL PROCESSING”, filed Nov. 12, 1999, by Laurence B. Boucher et al., now U.S. Pat. No. 6,247,060 which in turn claims the benefit under 35 U.S.C. .sctn.119(e)(1) of the Provisional Application filed under 35 U.S.C. .sctn.111(b) entitled “INTELLIGENT NETWORK INTERFACE CARD AND SYSTEM FOR PROTOCOL PROCESSING,” Ser. No. 60 / 061,809, filed on Oct. 14, 1997.[0002]This application also claims the benefit under 35 U.S.C. .sctn.120 of U.S. patent application Ser. No. 09 / 384,792, entitled “IN...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H04L12/56H04L29/06G06F5/10H04L45/243H04L49/901H04Q3/00
CPCG06F5/10H04L69/18H04L29/12009H04L29/12018H04L45/00H04L45/245H04L49/90H04L49/901H04L49/9063H04L49/9094H04L61/10H04Q3/0029H04L67/34H04L69/16H04L69/166H04L67/325H04L67/10H04L67/327H04L69/22H04L69/161H04L69/163H04L69/162H04L69/165H04L69/168H04L61/25H04L69/169H04L29/06H04Q2213/13093H04Q2213/13103H04Q2213/13204H04Q2213/13299H04Q2213/1332H04Q2213/13345H04L69/08H04L69/12H04L69/32H04L61/00H04L9/40H04L67/62H04L67/63
Inventor BOUCHER, LAURENCE B.BLIGHTMAN, STEPHEN E. J.CRAFT, PETER K.HIGGEN, DAVID A.PHILBRICK, CLIVE M.STARR, DARYL D.
Owner ALACRITECH
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