Multi-state EEPROM having write-verify control circuit
a control circuit and multi-state technology, applied in static storage, digital storage, instruments, etc., can solve the problems of longer time required for write operation, inability to perform write operation at high speed, and inconvenient design of conventional verification circuit for multi-value storing operation. achieve the effect of high speed
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first embodiment
[0088]FIG. 1 is a block diagram showing the schematic arrangement of a NAND-cell EEPROM according to the present invention.
[0089]A bit line control circuit 2 for controlling a bit line in a read / write operation and a wound line drive circuit 7 for controlling a word line potential are arranged for a memory cell array 1. The bit line control circuit 2 and the word line drive circuit 7 are selected by a column decoder 3 and a row decoder 8, respectively. The bit line control circuit 2 receives and outputs read / write data from / to an input / output data conversion circuit 5 through a data input / output line (IO line). The input / output data conversion circuit 5 converts readout multivalue information of a memory cell into binary information to externally output the multivalue information, and converts the binary information of externally input write data into the multivalue information of a memory cell. The input / output data conversion circuit 5 is connected to a data input / output buffer 6 ...
second embodiment
[0131]FIG. 11 shows the detailed arrangements of a memory cell array 1 and a bit line control circuit 2 in a NOR-cell EEPROM according to the present invention. A NOR cell is constituted by only a memory cell M10. One terminal of the NOR cell is connected to a bit line BL, and the other terminal is connected to a common ground line. Memory cells M which share one control gate WL constitute a page. Each of the memory cells M stores data at a threshold voltage Vt thereof. The memory cell stores data “0” indicating that the threshold voltage Vt is not less than Vcc, stores data “1” indicating that the threshold voltage Vt is lower than Vcc and not less than 2.5 V, and stores data “2” indicating that the threshold voltage Vt is lower than 2.5 V and not less than 0 V. One memory cell can have three states, and nine combinations can be obtained by two memory cells. Of these nine combinations, eight combinations are used, and data of three bits are stored in the two memory cells. In this e...
third embodiment
[0159]FIG. 20 shows a memory cell array 1 of a NAND-cell EEPROM according to the present invention. The memory cell array 1 is formed on a p-type well or a p-type substrate, and eight memory cells M1 to M8 are connected in series between a selection transistor S1 connected to a bit line BL and a selection transistor S2 connected to a common source line Vs, thereby constituting one NAND cell. The selection transistors S (S1 and S2) have selection gates SG (SG1 and SG2), respectively. The memory cells have floating gates (charge accumulation layers) and control gates CG (CG1 to CGS) which are stacked and formed on each other. The memory cells store information by using amounts of charges accumulated in the floating gates of the memory cells. The amounts of accumulated charges can be read out as the threshold voltages of the corresponding memory cells.
[0160]In the present invention, such a threshold voltage is read out as shown in FIGS. 21A and 21B. In this case, the memory cell M2 hav...
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