Interrupt signal control system and control method

Abstract

The invention is a kind of interrupt signal control system and method set and applied in the computer system. The computer system has a centre processor, a north bridge chip, a south bridge chip, the first outer devices and the second outer device. The interrupt signal control system includes: the first output and input interrupt control device; the second output and input interrupt control device and an interrupt state instructing path. The control method includes: a wakening signal is generated to the south bridge chip according to the ignition of the first interrupt signal sent by the first outer device connected to the south bridge chip, thus the south chip releases the electricity-saving state of the centre processor; an interrupt state instructing information is generated according to the ignition sent by the second outer device connected to the north bridge chip electrically; the interrupt state instructing information is transmitted to the south bridge chip through an interrupt state instructing path, thus the south bridge chip can release the electricity-saving state of the centre processor.

Description

technical field [0001] The invention relates to an interrupt signal control system and control method, in particular to an interrupt signal control system and control method set and applied in a computer system. Background technique [0002] The power-saving mechanism is widely used in computer systems, and the power-saving modes applied to the central processing unit (CPU) are divided into quite a few levels and types (such as Advanced Configuration and Power Interface (Advanced Configuration and Power Interface, C1, C2, and C3 modes defined in the ACPI) specification), but its purpose is nothing more than to reduce energy consumption and provide a lower temperature stable circuit operating environment. And under the general structure (please refer to the common computer system structure schematic diagram shown in Fig. 1), the mechanism that the central processing unit (CPU) 1 of computer system returns to normal operation from power-saving mode is by the south bridge in th...

AI Technical Summary

Problems solved by technology

[0011] However, when the central processing unit 1 is in the power-saving mode of C2 or C3 and the second peripheral device 6 sends an interrupt signal (interrupt) to the computer peripheral connection bus bridge device (PCI to PCI Bridge) 5 through an interrupt signal pin 60 After receiving the interrupt signal, the second output input advanced programmable interrupt controller (IO APIC) 50 in the computer peripheral connection bus bridge device (PCI to PCI Bridge) 5 will also send a message signal interrupt (message signaled interrupt, referred to as MSI ), and an interrupt message (interrupt message) exists in the form of a memory write instruction (memory write cycle), but since the destination of the interrupt message is the same as the central processing unit 1, the interrupt message only passes through the north bridge chip 3 and the data bus between the central processing unit 1 is transmitted to the central processing unit 1, but cannot be transmitted to the south bridge chip 2 to trigger the stop clock control module (STPCLK control module) 20 to remove (de-assert) the generated stop clock Signal (STPCLK#)

Therefore, in this new generation system state, the second peripheral device 6 connected to the computer peripheral connection bus bridge device (PCI to PCI Bridge) 5 cannot effectively wake up the computer system from the power saving mode and return to the normal operating mode.

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