Methods and apparatus for retiming and realigning SONET signals
A technique for retiming, signaling, used in telecommunications
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[0022] Turning now to FIG. 1 , a device 10 according to the present invention includes three FIFOs, preferably implemented in dual port RAM 12 , a write address generator 14 , a read address generator 16 , and a FIFO depth measurement circuit 18 . The RAM 12 has a data input WD (write data), a data output RD (read data), an address input WA (write address), an address output RA (read address), and a write enable input WE. Write address generator 14 receives input from a write demultiplexer (not shown) involving data for the three SPEs, SPE1, SPE2 and SPE3 and provides outputs to the WA and WE inputs of RAM 12. The read address generator receives input from a multiplexer (not shown) related to the read of data from SPE1, SPE2 and SPE3 and provides an output to the RA input of RAM 12.
[0023]The FIFO depth measurement circuit 18 includes a First_Byte detector 20 , a synchronizer 22 , three FIFO depth counters 24 and three FIFO depth latches 26 . First_Byte detector 20 receives...
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