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Self-adapting bandwidth phase locked loop with feedforward frequency divider

A phase-locked loop and frequency divider technology, applied in the field of phase-locked loops, can solve the problems of shrinking the available range of VCO control voltage and so on

Active Publication Date: 2008-06-18
LATTICE SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the supply voltage shrinks below 1.2V (volts), the usable range of the VCO control voltage shrinks significantly
On the other hand, the PLL application space continues to expand, requiring even wider frequency ranges for a single PLL

Method used

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  • Self-adapting bandwidth phase locked loop with feedforward frequency divider
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  • Self-adapting bandwidth phase locked loop with feedforward frequency divider

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Embodiment Construction

[0023] In certain embodiments, the invention relates to an adaptive bandwidth PLL with a wide frequency range. As just one example, in some implementations the frequency range is 500:1, but other ratios are possible. In some embodiments, the frequency range is extended with a dual PLL architecture that dynamically adjusts the division factor of the feed-forward divider.

[0024] FIG. 1 shows a PLL 10 with a phase frequency detector (PFD) 10, a charge pump (CP) / loop filter (LF) 16, and a voltage controlled oscillator (VCO) 22 with a division factor N. An output frequency control circuit 20 of a feedforward frequency divider (FF Div) 24, and a feedback frequency divider (FB Div) 28 with a frequency division factor M. VCO 22 provides a frequency f VCO the VCO signal. FF Div 24 offers a frequency f OUT The output clock signal (out clk) of and provides this signal to FB Div 28. The output of FB Div 28 is provided as input to PFD 14 . The charge pump and loop filter of the CP / ...

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Abstract

In some embodiments, a chip includes first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors. The chip also includes phase locked loop control circuitry to select the first and second division factors. Other embodiments are described and claimed.

Description

technical field [0001] Embodiments of the invention generally relate to phase locked loops. Background technique [0002] Phase locked loops (PPLs) are commonly used in integrated circuit chips and systems to generate a signal having a frequency and phase related to an input signal called a reference signal. The reference signal is generally a clock signal. The output signal of the PLL is also typically a clock signal that is "locked" to the input reference clock signal. PLLs are used in many types of chips including microprocessors, communications and other electronic devices. [0003] A typical PLL includes a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF) (which can be a low-pass filter), a voltage-controlled oscillator (VCO), and a frequency divider circuit. The PFD compares the phase of the reference signal with the feedback signal from the frequency divider circuit. Depending on the relationship of the phases of the reference signal and the f...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/18
CPCH03L7/0995H03L7/093H03L7/0895H03L7/23H03L7/08
Inventor J·金D-K·郑
Owner LATTICE SEMICON CORP