Dynamic latency map for memory optimization

Abstract

In a method of controlling computer-readable memory that includes a plurality of memory locations, a usage frequency of a plurality of data units is determined. Upon each occurrence of a predefined event, a memory latency for each of the plurality of memory locations is determined. After the predefined event, a data unit with a high usage frequency is stored in a memory location with a low latency.

Description

technical field [0001] The present invention relates to computer memory management, and more particularly, to computer architectures that store data units based on known memory location delays. Background technique [0002] Virtually all computer circuits employ some kind of digital memory to store data. Such memory may comprise a combination of different types of memory devices, including one or more of the following: on-chip memory (such as register arrays), on-board memory (such as cache memory), main memory (such as DRAM memory chips on a circuit board), flash memory (such as a memory device that can be plugged into a dedicated reader or a USB port), and magnetic disk storage (such as a hard drive). [0003] Certain data units residing in a memory space (which may include any method of grouping data) are used less frequently than other data units stored in the same memory space. However, different parts of a computer's memory space exhibit different memory latencies (t...

AI Technical Summary

Problems solved by technology

For example, when several connected memory locations are used for infinite loop computations, other nearby memory locations may experience increased latency due to local traffic on the memory bus serving the memory locations

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