Scanning chain diagnosis vector generation method and device and scanning chain diagnosis method

A technology for generating devices and scan chains, which is applied in the field of scan chain diagnosis and can solve problems such as misdiagnosis of combinational logic
CN101285871BActive Publication Date: 2010-07-28INST OF COMPUTING TECH CHINESE ACAD OF SCI
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Patents(China)
Current Assignee / Owner
INST OF COMPUTING TECH CHINESE ACAD OF SCI
Publication Date
2010-07-28

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Abstract

The invention provides a method and a device for generating scanning chain diagnostic vector and a diagnostic method of a scanning chain. The method for generating diagnostic vector comprises the following steps that: the failure type of a scanning chain is determined; a constraint condition is set according to the failure type of the scanning chain; under the constraint condition, the logic state of a scanning unit can obtain maximum transmitted output or false output number through a path formed by combinational logic, thereby generating scanning chain diagnostic vector. The device for generating diagnostic vector comprises the following parts: a failure type distinguishing unit used to judge the failure type of a scanning chain, a constraint condition unit used to set a constraint condition according to a failure type and a diagnostic vector generating unit used to ensure that the logic state of a scanning unit can obtain maximum transmitted output or false output number through a path formed by combinational logic so as to generate scanning chain diagnostic vector. The method and the device can effectively tolerate the failure in combinational logic without bringing hardware spending to a circuit.
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Description

technical field

[0001] The invention relates to a fault location method for a logic integrated circuit, in particular to a diagnostic vector generation method and device for a scan chain fault in a logic integrated circuit and a scan chain diagnosis method. Background technique

[0002] Scan technology is a widely used structured design for testability (Design ForTestability, DFT) technology. Scan-based logic diagnosis has become an indispensable means of mass production acceleration phase (yieldramp-up). Logical diagnosis can help failure analysis equipment quickly find the defect location that causes failure, thereby accelerating the failure analysis process.

[0003] The scan technology is to insert a shift register structure called a scan chain into the logic integrated circuit. Through the scan chain, the effective transmission of test data and the effective export of the internal state of the chip can be realized very conveniently.

[0004] The logic integrated circu...

Claims

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