Method and apparatus for decoding Turbo code
A decoding device and decoding technology are applied in the field of channel decoding, which can solve the problems of poor decoding performance and large decoding complexity, and achieve the effects of reduced decoding complexity and flexible and diverse use.
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Embodiment 1
[0085] In this embodiment, the interleaving processing unit includes two interleavers and a first information processing unit, and the first information processing unit is composed of two operators and a multiplier, wherein an operator and a multiplier are located in the interleaver On the input side of Interleaver 2, an operator is located on the output side of Interleaver 2 and Interleaver 1. The deinterleaving processing unit includes two deinterleavers and a second information processing unit, and the second information processing unit is composed of an operator and a multiplier, wherein an operator and a multiplier are located at the input of the deinterleaver 1 side.
[0086] Figure 7 Among them, Le1 corresponds to the additional information (extrinsic information) of the system bits (A, B), including the values corresponding to the system bits (A, B) are (0, 0), (0, 1), (1 , 0), (1, 1) four kinds of additional information. Le2 corresponds to the additional informa...
Embodiment 2
[0091] In this embodiment, the interleaving processing unit includes an interleaver and a first information processing unit, and the first information processing unit is composed of two operators and a multiplier, wherein the two operators and a multiplier are located in the interleaving input side of the device. The deinterleaving processing unit includes two deinterleavers and a second information processing unit, and the second information processing unit is composed of an operator and a multiplier, wherein both the operator and the multiplier are located at the end of the deinterleaver 1 input side.
[0092] Such as Figure 8 As shown, this embodiment is an optimized solution of the first embodiment, using one double-layer interleaver and two double-layer deinterleavers with the same structure, and using one less interleaver than the first embodiment. In the decoding process of this embodiment, Le1 is first weighted, that is, multiplied by coefficient α, then added to RU...
Embodiment 3
[0095] In this embodiment, the interleaving processing unit includes an interleaver and a first information processing unit, and the first information processing unit is composed of two operators and a multiplier, wherein the two operators and a multiplier are located in the interleaving input side of the device. The de-interleaving processing unit includes two de-interleavers and a second information processing unit, and the second information processing unit is composed of an operator and a multiplier, wherein the operator and the multiplier are respectively located at the ends of the de-interleaver 1 input side and output side.
[0096] Such as Figure 9 As shown, this embodiment is an optimized solution of Embodiment 1, using one double-layer interleaver and two double-layer deinterleavers with the same structure. In the decoding process of this embodiment, Le2 is deinterleaved first, and then weighted, that is, multiplied by coefficient β to obtain W1.
[0097] Other c...
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