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Timer implementing method and apparatus

An implementation method and timer technology, applied in the direction of generating/distributing signals, etc., to achieve the effect of a reliable timer mechanism

Active Publication Date: 2009-07-08
NEW H3C TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there is no solution in the prior art to provide an efficient and reliable timer mechanism for the data plane in an asymmetric multi-core processing system

Method used

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  • Timer implementing method and apparatus
  • Timer implementing method and apparatus
  • Timer implementing method and apparatus

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Embodiment Construction

[0023] figure 1 It is a flowchart of a method for implementing a timer according to an embodiment of the present invention. Such as figure 1 As shown, the method includes the following steps:

[0024] Step 101, any first data plane CPU acquires a new timer data structure in the timer idle linked list of the target data plane CPU, and sets timer parameters in the timer data structure; wherein the first data plane CPU The set timer parameters include the identification of the target data plane CPU.

[0025] In this step, the first data plane CPU and the target data plane CPU may be the same CPU or different CPUs. This is because, in the business process, various business processes may be processed on different cores, and different stages of a message may also be performed on different cores. Therefore, different data plane CPUs need to process the same a business flow. For example, CPU A on the data plane classifies received packets, sends packets belonging to a certain ses...

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Abstract

The invention discloses a realizing method and a device for a timer. The method comprises that: a first data plane CPU acquires a new timer data structure in a timer idle chain table of a target data plane CPU, and sets a timer parameter in the timer data structure, wherein the timer parameter set by the first data plane CPU comprises a mark of the target data plane CPU; the first data plane CPU sends out a timer creation message to a control plane CPU; the timer creation message carries a timer mark corresponding to the timer data structure; and after receiving the timer creation message, the control plane CPU finds the timer data structure according to the timer mark in the timer creation message, and adds the timer data structure into a timer running chain table of the target data plane CPU. The technical proposal provides an efficient and reliable timer mechanism for the data plane in an asymmetrical multi-core processing system.

Description

technical field [0001] The invention relates to the technical field of multi-core processing systems, in particular to a method and device for realizing a timer in a multi-core processing system. Background technique [0002] At present, in a multi-core network communication device, an asymmetric processing structure in which a data plane and a control plane are separated is generally adopted. That is, the control plane runs on one or more CPUs, and runs a complete embedded operating system, with complete multi-task management, interrupt management, time management and timer management, etc.; the data plane runs on other CPUs, There is no operating system or very simple resource management is provided, usually only simple data stream processing and forwarding work, and cannot provide the software timer mechanism that is often used in protocol software. [0003] As the complexity of business processing increases, it is inevitable to create and delete timing operations on the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/04
Inventor 柏林
Owner NEW H3C TECH CO LTD
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