Unlock instant, AI-driven research and patent intelligence for your innovation.

System and method for testing memory interference

A technology that interferes with testing and memory. It is applied in the detection of faulty computer hardware, etc., and can solve problems such as time consumption and long memory reading and comparison.

Inactive Publication Date: 2009-09-09
INVENTEC CORP
View PDF4 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, with the existing memory write interference test, it is necessary to read the entire memory for content comparison after each memory address is written, so it takes a long time to read and compare the memory
Therefore, the write interference test of the existing memory needs to be improved

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • System and method for testing memory interference
  • System and method for testing memory interference
  • System and method for testing memory interference

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0021] The present invention is a system and method for memory interference testing, which is mainly used to test memory products, and uses the method of writing back and forth and interpreting the storage content in the memory area of ​​the memory to test out memory interference. bad memory. In the following, the preferred embodiment of the memory interference testing system of the present invention will be firstly described with reference to the diagrams, and then the method and technology of the present invention will be applied to describe the steps of the present invention in detail.

[0022] With reference figure 1 , is a system block diagram of the memory interference test of the present invention. As shown in the figure, the memory interference testing system 100 proposed by the present invention at least includes a memory 110 , a shift unit 120 , a writing unit 130 , a reading unit 140 , and a judging unit 150 . The memory 110 has a plurality of storage areas 1101-1...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a system and a method for testing memory interference. The system for test memory interference at least comprises a memory, a transfer unit, a writing unit, a read-out unit and a determination unit. The direction of each storage area to be tested is sequentially transferred to next storage area by the transfer unit, and the storage content is repeatedly written in and interpreted aiming at each storage area so as to determine a bad memory with write-in interference.

Description

technical field [0001] The present invention relates to a system and method for memory interference testing, in particular to a system and method for discriminating bad memory with write interference by applying round-trip testing. Background technique [0002] The general test method of memory is to write a content to a certain address, and then read back the content of the memory unit for comparison. However, if it is a bad memory, the memory units will interfere with each other during the writing process. For example, when writing to a certain address, the content of another address will also be changed. [0003] The existing test method for memory write interference is to read out the contents of other memory addresses for judgment after writing to one memory address. However, in the existing memory write interference test, after each memory address is written, the entire memory must be read for content comparison, so it takes a long time to read and compare the memory....

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F11/22
Inventor 陈志伟卢晓芬
Owner INVENTEC CORP