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Memory and reading method thereof

A memory and storage unit technology, applied in static memory, read-only memory, digital memory information and other directions, can solve problems such as disturbance, smaller read interval, and read disturbance.

Inactive Publication Date: 2010-02-03
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, due to the second-bit effect, the threshold voltage of the right half cell 120 will be affected by the threshold voltage of the left half cell 110, so that the reading interval becomes smaller and the right half cell 120 will be read. generate error
In addition, if the bit line voltage or word line voltage used for reading is too high, it may affect the low threshold voltage of the left half cell 110, resulting in read disturbance (read disturbance) when the left half cell 110 is read. The phenomenon

Method used

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Embodiment Construction

[0023] The present invention provides a method for reading a memory and a memory. By judging the threshold voltage of adjacent half cells, different voltages are used to read the data stored in the target half cell, so that the reading can be enlarged. Interval (read window) and reduce read disturbance (read disturbance).

[0024] In the following embodiments of the present invention, the memory is a multi-level cell memory and the storage unit is a multi-level unit as an example for illustration, but it is not limited thereto.

[0025] Please refer to figure 2 , which is a flow chart of a memory reading method according to a preferred embodiment of the present invention. The memory reading method disclosed in this embodiment is actually applied to a multi-level cell (MLC) memory. This multi-level cell memory includes a plurality of memory cell blocks, and each memory cell block includes a plurality of multiple The level units, each multi-level unit includes a left half uni...

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Abstract

A method for reading a memory, which includes a memory cell having a first half cell and a second half cell, includes the following steps. A first voltage is applied to the memory cell to determine whether a threshold voltage of the first half cell is higher than a predetermined value or not. If the threshold voltage of the first half cell is higher than the predetermined value, a second voltage higher than the first voltage is applied to the memory cell to read data stored in the second half cell, otherwise a third voltage lower than the first voltage is applied to the memory cell to read thedata stored in the second half cell.

Description

technical field [0001] The present invention relates to a memory reading method and memory, and in particular to a memory reading method and memory capable of expanding the reading interval and reducing reading disturbance. Background technique [0002] Memory is used for a variety of data storage purposes today. The memory includes various types, such as multi-level cell (Multi-Level Cell, MLC) memory and the like. Please refer to Figure 1A , which shows a schematic diagram of a conventional multi-level unit. The multi-level unit 100 includes a left half unit 110 and a right half unit 120 . Each half-cell of the multi-level cell 100 may have multiple bits according to different threshold voltage distributions. [0003] Here we take each half-unit with 2 bits as an example for illustration, please refer to Figure 1B , which shows the distribution diagram of the threshold voltage distribution of the multi-level cell 100 . Wherein, the threshold voltage distributions of...

Claims

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Application Information

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IPC IPC(8): G11C16/26G11C16/30
CPCG11C2211/5612G11C16/0475G11C16/26G11C11/5671
Inventor 洪俊雄何信义
Owner MACRONIX INT CO LTD