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Sdram convolutional interleaver with two paths

A technology of interleaver and path, applied in the field of data communication, to achieve the effect of optimizing access time, increasing speed, and optimizing SDRAM access

Active Publication Date: 2010-02-17
IMAGINE COMM
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

(However, SRAM should not be confused with ROM and Flash memory because it is volatile and retains data only as long as power is continuously applied

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  • Sdram convolutional interleaver with two paths
  • Sdram convolutional interleaver with two paths
  • Sdram convolutional interleaver with two paths

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Embodiment Construction

[0147] According to the present invention, in general, two (2) path interleavers are built with multiple channels, and each channel can go through short path or long path due to channel classification in SRAM and perform at high speed. Furthermore, interleaving writes to SRAM allows the SRAM to be smaller, which is beneficial when implemented in an FPGA. Additionally, the writes are packed to support many interleaver modes for small SRAMs. The technique disclosed herein supports dual SDRAM with two interleaver lengths without causing significant slowdown.

[0148] The present invention makes it possible to implement an SDRAM convolutional interleaver in two paths (A and B) by using SDRAM, FPGA logic, and FPGA SRAM.

[0149] The problem solved by the present invention is that burst writes to SDRAM two-path interleaver will reach a maximum (limited thereto) at a throughput of 10M symbols / sec and require higher symbol rates (e.g. 110M symbols / sec ).

[0150] According to the p...

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Abstract

An SDRAM convolutional interleaver with two paths. Symbols are assigned to a given one of the two paths, then are sorted to minimize (to one) a number of breaks in a sequential Interleaver write address. After sorting, the symbols are stored staggered in SRAM and burst written to SDRAM. Before writing to SDRAM, data is accumulated for four symbols at a time, and the data is written four symbols wide to optimize SDRAM access time. 8 bit symbols are written 32 bits at a time to SDRAM.

Description

technical field [0001] The present invention relates to data communications, more particularly to error correction techniques, and more particularly to convolutional interleaving. Background technique [0002] The world is going digital. Cell phone communications are examples of digital signal communications, and satellite broadcasts are often digital. Many wired telephone connections are still analog, as is most television broadcasting, however these mediums will also go digital, and it is not inconceivable that the use of analog signals for communication will largely become a thing of the past. [0003] Concurrent with the "digital revolution," the world is going wireless. A mobile phone is an example of wireless communication. [0004] Several expertise and aspects of technology have developed throughout the field of digital communications, including error detection and correction techniques, to name a few. [0005] "Decoding" is a term that usually comes up in any di...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/00
CPCH03M13/15H03M13/2732H03M13/1515
Inventor 约尔延·安德松
Owner IMAGINE COMM