Active component array substrate and manufacturing method thereof
A technology of active components and array substrates, applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve problems such as deterioration of display quality, and achieve the effect of improving liquid crystal dislocation
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no. 1 example
[0052] figure 2 is a schematic top view of the active device array substrate according to the first embodiment of the present invention, and 3A to 3H It is a schematic cross-sectional view of the manufacturing method of the active device array substrate according to the first embodiment of the present invention, wherein 3A to 3H The left side of is a schematic cross-section along the II-II' section line, and 3A to 3H The right side of is a schematic cross-sectional view along the III-III' section line.
[0053] First, please refer to figure 2 and Figure 3H The active element array substrate 200 of this embodiment includes a substrate 210 , a plurality of scan lines 220 arranged on the substrate 210 , a plurality of data lines 230 arranged on the substrate 210 , and a plurality of active elements 240 arranged on the substrate 210 , a first protective layer 250, a transparent lining layer (or called a transparent barrier wall) 260, a plurality of color filter layers 27...
no. 2 example
[0069] Figures 4A to 4J It is a schematic cross-sectional view of a manufacturing method of an active device array substrate according to a second embodiment of the present invention. The manufacturing method of the active device array substrate of this embodiment is similar to the structure and manufacturing method of the active device array substrate of the first embodiment, but the main difference between the two lies in the structure and process of the active device 240 . The manufacturing method of the active element 240 of this embodiment will be described in detail below.
[0070] First, please refer to Figure 4A , forming a first patterned conductive layer on the substrate 210 , wherein the first patterned conductive layer includes a plurality of scan lines 220 and a plurality of gates 240G connected to the scan lines 220 . Preferably, in this embodiment, the first patterned conductive layer further includes a shared / shared electrode line (not shown) parallel to th...
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