Interrupt nesting method for transplanting muCOS-II to ARM7

A nesting and mode technology, applied in the direction of program startup/switching, multi-program installation, etc., can solve problems such as program running errors, sub-functions cannot return correctly, and achieve the effect of avoiding errors

Active Publication Date: 2012-09-26
NO 513 INST THE FIFTH INST OF CHINA AEROSPACE SCI & TECH
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there is a special case for the value of the connection register (LR), that is, the first-level interrupt processing includes calling a subfunction-jump instruction (BL), and the second instruction occurs just after the execution of the BL instruction is completed. Level interrupt, because the return address is saved in LR when the BL instruction is executed, and the return address after the second-level interrupt is saved in LR when the processor responds to the second-level interrupt. Two consecutive save operations make the return of the BL instruction The address is overwritten, so that the sub-function called in the first-level interrupt cannot return correctly, causing the program to run incorrectly

Method used

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  • Interrupt nesting method for transplanting muCOS-II to ARM7
  • Interrupt nesting method for transplanting muCOS-II to ARM7

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Embodiment Construction

[0035] The present invention will be described in detail below with reference to the accompanying drawings and examples.

[0036] In order to realize interrupt nesting and ensure the correctness of program operation when interrupt nesting occurs, the program design must solve two key problems:

[0037] a. Before the next-level interrupt is enabled, the site information of the previous-level interrupt must be protected. The site information mainly includes LR, CPSR, R0~Rn. This problem is easier to implement, just push the information to be protected into the stack.

[0038] b. Protect the BL during the interrupt processing to prevent it from returning correctly when sub-functions are called during the interrupt.

[0039] Based on this, the present invention provides an interrupt nesting method transplanted from μCOS-II to ARM7. The basic idea is to change the processor mode before re-enabling the interrupt, and use the LR in the non-interrupt mode to record the BL instruction...

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Abstract

The invention discloses an interrupt nesting method for transplanting muCOS-II to ARM7, which comprises the following steps: changing the mode of a processor before re-enabling interrupts, and adopting an LR in an uninterruptible mode to record a return address used by a BL command. Thus, when a new interrupt occurs, the interference of an LR register can not be caused, so the subfunction called in the interrupt can be accurately returned. The invention can ensure the accuracy of program run when the interrupt nesting appears.

Description

technical field [0001] The invention relates to the technical field of software design, in particular to an interrupt nesting method for transplanting μCOS-II to ARM7. Background technique [0002] The μCOS-II operating system is a complete, portable, curable, tailorable, preemptive, deterministic, preemptive real-time multitasking kernel. It always runs the highest priority ready task. The source code of μCOS-II is open, and the number of interrupt nesting layers can reach 255. The V2.80 version can already manage 255 tasks, and the number of source code lines is only about 5000 lines. Considering the requirements of reliability, stability, strong real-time performance and resources in some fields, the μCOS-II operating system can be transplanted into electronic equipment for task management. [0003] Moreover, many electronic devices need to realize the requirements of low power consumption, miniaturization and high performance at present, so it can be realized by transp...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/48
Inventor 宋庆国宋光磊占丰刘中伟
Owner NO 513 INST THE FIFTH INST OF CHINA AEROSPACE SCI & TECH
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