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Semiconductor package with sectioned bonding wire scheme

A technology for packaging components and semiconductors, which is applied in the fields of semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., which can solve the problems of high time and cost, and the cost of UV glue materials is not cheap.

Inactive Publication Date: 2011-04-27
NAN YA TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the time and cost of the mold cavity design and mold flow analysis mentioned above are high, while the method of using UV glue to fix the gold wire requires additional processes or equipment, and processing time, and the material cost of UV glue is not cheap

Method used

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  • Semiconductor package with sectioned bonding wire scheme
  • Semiconductor package with sectioned bonding wire scheme
  • Semiconductor package with sectioned bonding wire scheme

Examples

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Embodiment Construction

[0051] See figure 1 , Which is a schematic top view of a semiconductor packaging component according to a preferred embodiment of the present invention. Such as figure 1 As shown, the semiconductor packaging member 1a includes a substrate 10, such as a packaging substrate. A semiconductor chip 20 and a film sealing material 30 are provided on the upper surface of the substrate 10, which at least cover the semiconductor chip 20.

[0052] According to a preferred embodiment of the present invention, at least two rows of lead fingers 12a-12d and 14a-14d are provided on the upper surface of the substrate 10. According to a preferred embodiment of the present invention, the lead fingers 12a-12d are arranged in a straight line along the reference y-axis on one side of the semiconductor chip 20, and the lead fingers 14a-14d are arranged on the other side of the semiconductor chip 20 relative to the lead fingers 12a-12d. One side is aligned along the reference y axis.

[0053] According t...

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PUM

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Abstract

A semiconductor package with sectioned bonding wire scheme includes a carrier substrate having thereon at least one bond finger; a semiconductor chip mounted on the top surface of the carrier substrate; at least one active bond pad disposed on the semiconductor chip; at least one dummy bond pad disposed on the semiconductor chip; a first bonding wire electrically connecting at least one active bond pad and the at least one dummy bond pad; a second bonding wire electrically connecting at least one dummy bond pad and the at least one bond finger; and a molding compound encapsulating at least the semiconductor chip.

Description

Technical field [0001] The present invention relates to the technical field of semiconductor packaging, in particular to an improved semiconductor integrated circuit packaging component, which adopts a segmented gold wire structure, so that the gold wire has strong strength support and avoids the problem of gold wire falling off caused by mold flow impact. Background technique [0002] Dynamic Random Access Memory (DRAM) is mainly developed to meet the requirements of high capacity and high performance. The development of packaging technology for a single DRAM is based on the shortest internal path and 2-dimensional System-on-Chip (2D-SoC) solutions in the pursuit of high performance. However, the DRAM under the SoC architecture is insufficient in achieving high-capacity requirements. In order to meet the demand for high capacity, the industry has developed various DRAM stack packaging technologies, such as stack by wire bond, package-on-package, RDL-Wire bond, Vertical Interco...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/48H01L23/49H01L25/00
CPCH01L2224/48599H01L2224/05553H01L25/0657H01L2224/0401H01L2224/48227H01L23/49838H01L2924/15311H01L2924/014H01L2225/0651H01L23/3128H01L2924/0105H01L2924/01029H01L2224/48799H01L2224/45147H01L2924/00014H01L2224/0603H01L23/13H01L2224/45144H01L2924/01005H01L2924/01082H01L2924/01033H01L24/06H01L2924/01079H01L24/45H01L2224/4824H01L2224/48091H01L23/49816H01L2225/06565H01L2224/484H01L2224/73265H01L2224/05599H01L24/49H01L2225/06558H01L24/48H01L2224/32145H01L2224/4813H01L2224/4911H01L2224/85399H01L2924/14H01L2224/06135H01L2224/06136H01L2924/351H01L2924/181H01L24/73H01L2924/00012H01L2924/00
Inventor 陈仁君
Owner NAN YA TECH