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Semiconductor chip package

A packaging structure, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve the problems of mismatch, affecting the reliability of the packaging structure, delamination, etc.

Inactive Publication Date: 2011-05-18
NAN YA TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, due to the mismatch of Coefficient of Thermal Expansion mismatch (CTE) between the chip, the substrate and the packaging material in the known packaging structure, the packaging structure is susceptible to thermo-mechanical stress during operation. influences
This stress is very likely to cause delamination between the packaging material and the substrate, thereby affecting the reliability of the packaging structure.

Method used

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  • Semiconductor chip package
  • Semiconductor chip package
  • Semiconductor chip package

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Embodiment Construction

[0036] figure 1 It is a top view of a semiconductor package structure with anchor piles according to a preferred embodiment of the present invention. figure 2 according to the first preferred embodiment of the present invention figure 1 The side view of the semiconductor package structure with anchor piles along the direction A-A' in the figure. image 3 based on figure 1 A side view of the semiconductor package structure with anchor piles shown along the direction B-B' in FIG. Figure 4 It is a deformation of the anchor pile shown according to another preferred embodiment of the present invention.

[0037] Such as figure 1 , 2 , 3, the semiconductor package structure 10 includes a base 12, and the base 12 has an upper surface 14 and a lower surface 16. The substrate 12 may be a resin substrate, a glass substrate, a semiconductor substrate, or a metal substrate. The above-mentioned upper surface 14 includes a chip installation area 18 and an anchor pile installation ar...

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PUM

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Abstract

A semiconductor chip package includes a base comprising a die attach region and a mold-lock forming region surrounding the die attach region; a die mounted onto the base within the die attach region; a plurality of line-shaped trenches in the mold-lock forming region; a mold body encapsulating the die; and a mold lock inlaid in each of the line-shaped trenches to securely interlock the mold body to the base.

Description

technical field [0001] The present invention relates to a semiconductor packaging structure, in particular to a packaging structure which utilizes mold-locks to fix the packaging material on the substrate and avoid delamination of the packaging material. Background technique [0002] In the process of the known semiconductor package structure, it generally includes electrically connecting and adhering the chip to the substrate. Usually the aforementioned chips are covered by encapsulation materials, the main purpose of which is to: avoid contact between the chip and air and water vapor, avoid excessive chip temperature, provide pins for transmitting signals and power between the chip and the circuit board, and provide sufficient mechanical strength for the chip , so that the fragile chips can be processed later. Therefore, semiconductor packaging materials are a very important part of semiconductor packaging engineering. Whether the characteristics of packaging materials an...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/16
CPCH01L23/3121H01L23/13H01L2224/4824H01L24/48H01L23/3142H01L2924/00014H01L2924/14H01L2924/181H01L2924/00H01L2224/45099H01L2224/45015H01L2924/207
Inventor 陈仁君
Owner NAN YA TECH