Common-mode controlled inductance-capacitance voltage-controlled oscillator

Abstract

The invention discloses an inductance-capacitance voltage-controlled oscillator, which comprises negative resistance P-channel metal oxide semiconductor (PMOS) transistors M1 and M2, negative resistance N-channel metal oxide semiconductor (NMOS) transistors M3 and M4, an inductor L and an adjustable capacitor C, and is characterized in that: the inductance-capacitance voltage-controlled oscillator comprises a common-mode control circuit for controlling common mode points of oscillating signals VOSCP and VOSCN, wherein the common-mode control circuit comprises phase inverters U1 and U2, a compensating capacitor CC, a tail-current NMOS transistor MN, a tail-current PMOS transistor MP and a monitoring circuit. Compared with the traditional inductance-capacitance voltage-controlled oscillator, the common-mode controlled inductance-capacitance voltage-controlled oscillator successfully solves the problem that the output clock duty deviates 50 percent due to offset of negative resistance tube voltage-current transfer characteristics; therefore, good phase noise characteristics of a phase locked loop can be guaranteed.

Description

technical field [0001] The invention belongs to the field of semiconductor integrated circuit design, and in particular relates to an inductance-capacitance voltage-controlled oscillator. Background technique [0002] As one of the core modules of electronic systems, phase-locked loops are widely used in the fields of communication equipment, test instruments, computers and consumer electronics. In recent decades, due to the rapid development of microelectronics technology, modern electronic systems are also advancing towards high performance and high integration. Taking the wireless communication system as an example, with the approach of the 4G era, higher-speed broadband digital communication services are about to start. This puts higher demands on the radio frequency (RF) transceiver module, data conversion module (ADC / DAC) and digital processor (DSP) in the system. And all these modules need to work under the clock drive provided by the phase-locked loop, so the perfo...

AI Technical Summary

Problems solved by technology

This will seriously deteriorate the phase noise characteristics of the PLL

Not only that, the non-50% duty cycle clock will also deteriorate the common mode rejection characteristics of the circuit in some high-performance applications (such as high-speed high-precision ADC / DAC)

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