System for detecting trigger single particle effect in digital application specific integrated circuit

Abstract

The invention discloses a system for detecting trigger single particle effect in a digital application specific integrated circuit. The system comprises a master control computer, a programming logic device, a storage device, a transmission protocol device, wherein the programming logic device comprises a mode selection module, a vector generation module, an edge detection module, a level detection module, an error frame cache module and a transmission protocol module. According to the invention, an abundant trigger overturn phenomenon caused by clock circuit single particle overturn and a normal abundant trigger single particle overturn phenomenon are effectively distinguished, simultaneously combined with preservation data of the error frame cache module, a single particle overturn error rate of each trigger is accurately calculated. The system of the invention has the characteristics of simple composition and high detection precision.

Description

technical field [0001] The invention relates to a system for detecting the single event effect of a trigger in a digital application-specific integrated circuit, and belongs to the technical field of semiconductor device anti-space single event effect verification technology. Background technique [0002] When a digital circuit is applied in a space environment, space high-energy particles will penetrate the interior of the semiconductor device and generate ionization on the path, and the circuit nodes will absorb the electrons and holes generated by the ionization, resulting in circuit errors. This effect is called single event effect . The ability to verify the anti-single event effect of semiconductor devices on the ground mainly relies on ground heavy ion accelerators to simulate single-event tests. Since the test site needs to be carried out in a vacuum radiation environment, more requirements are put forward for the anti-interference, real-time performance, and volume ...

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Problems solved by technology

[0005] The existing detection system based on the scanning design method to verify the single event effect of the flip-flop in the digital ASIC chip mainly has the following two shortcomings: one is that the error rate of the flip-flop of the entire circuit chip can be calculated, but it is difficult to distinguish Counting the error rate of each flip-flop is not easy to identify and locate flip-flops that are sensitive to single events in digital ASIC chips, so it is not convenient for designers of radiation-resistant hardened chips to improve their designs; For the global or local clock circuit, once the clock circuit has a single event flip in the test, it will cause a large number of flip-flop flip errors. It is necessary to distinguish this situation from the normal flip-flop single event flip, and the existing detection system does not have this Function

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