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Storage device and relevant method

A storage device, storage unit technology, applied in information storage, static memory, read-only memory, etc., can solve problems such as the reduction of chip qualification rate

Inactive Publication Date: 2014-08-20
MSTAR SOFTWARE R&D (SHENZHEN) LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the pass rate of the chip will also be reduced due to the damage of the storage device.

Method used

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  • Storage device and relevant method
  • Storage device and relevant method
  • Storage device and relevant method

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0037] Please refer to figure 1 ; It shows an embodiment 10 of the storage device of the present invention. The memory device 10 can be arranged in a chip (not shown), and has a plurality of memory units arranged in a plurality of bit rows and a plurality of character columns respectively; figure 1 In the example, bit rows Y0 to Y11 are used to represent multiple bit rows, and character columns X0, X1 to Xm, and even XM are used to represent multiple character columns. Each bit column in the bit rows Y0 to Y11 has a plurality of storage units; the plurality of storage units in the same bit row correspond to the same row address, and respectively correspond to one of the character columns X0 to XM. For example, the storage units U(1, 2), U(m, 2) and U(M, 2) all correspond to the row address of the bit row Y2, and the storage units U(1, 3), U(m, 3 ) and U(M, 3) correspond to the row address of the bit row Y3. The storage units U(1,2), U(1,3), U(1,7) and U(1,8) in the bit rows...

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Abstract

The invention provides a storage device and a relevant method. A plurality of first bit rows for constructing a routine storage space for the storage device and at least one standby second bit row are arranged in the storage device, and row addresses of damaged first bit rows are recorded as preset row addresses. When one of character lines is read, data recorded in the first bit rows and the second bit row can be respectively latched in a first latching area and a second latching area, and when the latched read data are output by using the row addresses of the first bit rows as access row addresses in sequence, if the access row addresses accord with the preset row addresses, the data are output by the second latching area, and otherwise, the data are output by the first latching area.

Description

technical field [0001] The present invention relates to a storage device and a related method, in particular to a storage device and a related method capable of repairing / replacing damaged bit rows to improve yield. Background technique [0002] Chips are one of the most important hardware foundations of modern electronic systems. As the functions of the chip become more and more diverse and complex, an embedded storage device is often built in the chip to support the storage space required for the operation of the chip. However, the yield of the chip will also decrease due to the damage of the storage device. Contents of the invention [0003] The present invention proposes a repairable damaged storage device, so as to improve the pass rate of the storage device and even the whole chip. The storage units used to construct the conventional storage space in the storage device are arranged into a plurality of character columns and bit rows. According to practice, it can b...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/06
Inventor 谢文斌谢孟勋
Owner MSTAR SOFTWARE R&D (SHENZHEN) LTD