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Cryptographic apparatus and memory system

An encryption device and register technology, which is applied to encryption devices with shift registers/memory, transmission systems, digital transmission systems, etc., can solve problems such as performance degradation, encryption is not executed in parallel, and achieve the effect of improving speed.

Inactive Publication Date: 2012-04-11
TOSHIBA MEMORY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this case encryption is not performed in parallel and performance is degraded

Method used

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  • Cryptographic apparatus and memory system
  • Cryptographic apparatus and memory system
  • Cryptographic apparatus and memory system

Examples

Experimental program
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Effect test

Embodiment Construction

[0023] The configuration of a memory system including an encryption device according to an embodiment will be explained.

[0024] figure 1 is a block diagram of an exemplary configuration of the memory system 1 according to the present embodiment. The memory system 1 is configured to encrypt write target data and store the encrypted write target data in response to a write request from the host device 2, and to encrypt and store the encrypted and stored read target data in response to a read request from the host device 2. Encrypt and read. The memory system 1 can be realized as, for example, a NAND semiconductor memory device. Such as figure 1 As shown, the memory system 1 includes an encryption device 10 , a memory 50 and an interface unit 60 . The host device 2 is a computer that has the memory system 1 built therein, or that has the memory system 1 connected thereto externally. Write requests and read requests to the memory system 1 are issued by an operating system (...

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Abstract

The invention relates to a cryptographic apparatus and a memory system. According to one embodiment, the cryptographic apparatus includes: cryptographic cores ("cores"), an assigning unit, a concatenating unit, and an output controlling unit. If a CTS flag thereof is on, each core encrypts using a symmetric key cipher algorithm utilizing CTS, while using a symmetric key. When an input of a CTS signal is received, the assigning unit assigns first input data to a predetermined core and turns on the CTS flag thereof. The concatenating unit generates concatenated data by concatenating operation data generated during encrypting the first input data, with second input data that is input immediately thereafter. The output controlling unit controls outputting the concatenated data to the predetermined core, outputting first encrypted data obtained by encrypting the concatenated data, and over outputting second encrypted data obtained by encrypting the first input data, and further turns off the predetermined core's CTS flag.

Description

[0001] Cross References to Related Applications [0002] This application is based on and claims priority from Japanese Patent Application No. 2010-211727 filed on September 22, 2010; the entire contents of which are incorporated herein by reference. technical field [0003] Embodiments described herein generally relate to encryption devices and memory systems. Background technique [0004] Symmetric block ciphers are designed for the purpose of protecting electronic data. Block ciphers allow the encryption of a single data block of the block length of the cipher. When the data length is greater than the block length, the data must be split into independent cipher blocks. Thus, an encryption method that can hide data whose length is larger than the block length by using a symmetric block cipher encryption algorithm, and an encryption method for generating an authentication code that can be used to detect tampering of original data have been developed. This encryption meth...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/24
CPCH04L2209/125H04L9/0637H04L9/06H04L9/14
Inventor 藤崎浩一
Owner TOSHIBA MEMORY CORP