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Method for scheduling internal memory among multiple cores

A technology of memory scheduling and memory access, which is applied in the direction of multi-program device and resource allocation, etc., to prevent excessive waiting and reduce system delay

Active Publication Date: 2013-07-10
TSINGHUA UNIV
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  • Description
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Problems solved by technology

[0005] The technical problem to be solved by the present invention is: how to solve the memory fair scheduling problem among multiple cores

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  • Method for scheduling internal memory among multiple cores

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Embodiment Construction

[0026] A method for scheduling memory between multiple cores proposed by the present invention will be described in detail below with reference to the drawings and embodiments.

[0027] It is well known that the main body of the memory architecture includes memory row, bank, rank, and channel, and a memory access request needs to be accessed sequentially from row to channel.

[0028] The main work of the scheduling method is comprehensive scheduling, and then the memory access request to be executed is handed over to the bank scheduler for corresponding execution. After the bank buffer is executed, the channel buffer completes the final data transmission. Among them, cache refers to the high-speed buffer memory.

[0029] It is worth noting that the design of the present invention is still based on the traditional DDR2 controller, but when a request enters the memory controller, a labeling operation is added to record the enqueue time of the request. As fair scheduling, the ave...

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Abstract

The invention relates to the technical fields of computers and electronic information, and discloses a method for scheduling an internal memory among multiple cores. The method comprises the following steps: S1, obtaining internal memory access requests from the multiple cores, labeling the internal memory access requests, and then, placing the labeled internal memory access requests in a buffering area queue; S2, selecting one internal memory access request to execute from the ready buffering area queue according to a fair scheduling method; S3, selecting the internal memory access request with the longest waiting time from a bank buffering area, and submitting the internal memory access request to a channel buffering area; and S4, selecting the data of the request selected from the bankbuffering area in the step S3 from the channel buffering area, submitting the data to a cache, swapping out a row which is not accessed for a long time from the cache, and notifying a CPU (central processing unit) of obtaining the data. By using the method, the fair scheduling problem of the internal memory among the multiple cores can be solved.

Description

technical field [0001] The invention relates to the technical field of computers and electronic information, in particular to a multi-core memory scheduling method. Background technique [0002] In recent years, the development of computer has entered the multi-core era, and the multi-core technology of CPU has been vigorously developed. In the multi-core architecture of shared memory, multiple processors need to access the same part of system memory, so the importance of memory scheduling is becoming more and more obvious. It has become a research hotspot at home and abroad. [0003] In the current multi-core architecture, the form of shared memory is still used. During the execution of computer programs, memory needs to be accessed. At this time, a memory access request will be sent to the memory controller. Buffers such as row, rank, bank, and channel implement memory scheduling. In a shared-memory computer system, the memory needs to provide fair service to the multi-c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/50
Inventor 王瑀屏刘虎球赵鹏
Owner TSINGHUA UNIV
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