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Bit-by-bit upset fault injection method specifically for SRAM (static random access memory) type FPGA (field programmable gate array)

A fault injection and bit-by-bit technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problem that users cannot decide to flip bits, and achieve the effect of less time spent

Inactive Publication Date: 2013-04-24
BEIHANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In particular, the fault injection method using the reconfiguration feature of SRAM-type FPGA has received great attention, but there are still disadvantages that users cannot determine the flip bit according to the corresponding resource-sensitive bit

Method used

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  • Bit-by-bit upset fault injection method specifically for SRAM (static random access memory) type FPGA (field programmable gate array)
  • Bit-by-bit upset fault injection method specifically for SRAM (static random access memory) type FPGA (field programmable gate array)
  • Bit-by-bit upset fault injection method specifically for SRAM (static random access memory) type FPGA (field programmable gate array)

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0057] Adopt the bit-by-bit flipping fault injection method of the present invention to test the multiplier designed by TMR, place the voting device in the CLB15-20 column, and intercept the generated msk.dat file as figure 2 shown.

[0058] A bit of 1 in the msk.dat file means that the corresponding bit in the configuration data is a sensitive bit, and the last three bytes represent the total number of sensitive bits. Simply analyze the msk.dat file to get the specific location of the sensitive bit. The sensitive bit statistics of the CLB15-20 column of the TMR multiplier are as follows image 3 shown.

[0059] According to the experimental results, the reliability parameters of the circuit design are obtained: the dynamic flip section is 5.88E-13 / cm 2 / device; the failure rate is 9.50E-7 / day; the reliability curve is obtained as Figure 4 shown.

[0060] The test shows that the bit-by-bit flipping fault injection method of the present invention for SRAM FPGA can effect...

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Abstract

The invention discloses a bit-by-bit upset fault injection method specifically for an SRAM (static random access memory) type FPGA (field programmable gate array). Single event upset sensitive positions in a configuration memory unit of a circuit design are detected to obtain dynamic upset sections and failure rate, a reliability change curve is drawn, and accordingly reliability of space application of the circuit design can be evaluated. The method includes a first step, realizing initial configuration; a second step, upsetting bits; a third step, judging whether fault is generated or not; a fourth step, judging whether a test is completed or not; and a fifth step, acquiring the dynamic upset section and the reliability change curve of the FPGA.

Description

technical field [0001] The invention relates to a bit-by-bit flipping fault injection method based on SRAM type FPGA, which belongs to the technical field of FPGA space reliability. Background technique [0002] After a single-event upset occurs in the FPGA, its failure manifests itself as a change in the contents of memory cells in the FPGA, and the contents of these memory cells are determined by the bits in the configuration file. At present, radiation simulation is mainly used for single event upset in the simulated space on the ground, that is, heavy ions or high-energy protons and other simulated sources are used to irradiate the device, and the radiation sensitive parameters are tested for the selection of the device and the estimation of the actual radiation environment. The single event turnover rate provides the basis. [0003] If the method of radiation simulation is adopted, firstly, the irradiated devices can no longer be used, thus increasing the cost of the t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 潘雄张家铭朱明达李安琪宋镜明张忠钢宋凝芳
Owner BEIHANG UNIV