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Nonvolatile memory with enhanced efficiency for address asymmetric nvm cells

A technology of magnetic components and access transistors, applied in the direction of static memory, read-only memory, digital memory information, etc.

Active Publication Date: 2016-04-20
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Higher current requirements also dictate the size of the NMOS transistors and limit the scalability of the MRAM cell to smaller geometries

Method used

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  • Nonvolatile memory with enhanced efficiency for address asymmetric nvm cells
  • Nonvolatile memory with enhanced efficiency for address asymmetric nvm cells
  • Nonvolatile memory with enhanced efficiency for address asymmetric nvm cells

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Embodiment Construction

[0013] overview

[0014] The present disclosure relates to an STT-MRAM cell that incorporates a PMOS or p-type transistor as an access transistor to control the drive current supplied to the MTJ or magnetic memory element of the STT-MRAM cell. The MTJ switches between two magnetoresistive states based on the drive current provided by the PMOS transistor. In one example, the MTJ requires a higher current level to transition from the first state to the second state than the amount of current required to transition from the first state to the second state.

[0015] At higher current states or transitions, the MTJ operates under sub-optimal conditions due to higher current levels that may cause damage to the MTJ. However, PMOS transistors under higher current conditions are minimally affected by the receptor effect, which depends on the voltage difference between the transistor's source and substrate. Therefore, the PMOS transistor operates at an optimal state or condition dur...

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PUM

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Abstract

The present invention relates to non-volatile memory with enhanced efficiency for address asymmetric NVM cells. This application describes embodiments of MRAM cells that utilize PMOS transistors as access transistors. The MRAM cell is configured to mitigate the effect of applying an asymmetric current load to transition the magnetic tunnel junction of the MRAM cell between magnetoresistive states.

Description

Background technique [0001] Non-volatile memory (NVM) cells retain stored information without receiving constant or permanent power. NVM cells can provide significant power savings for electronic systems that do not require or provide constant power to the cell. Initialization time for electronic systems can also be reduced via NVM. For example, instructions stored in NVM are ready to execute and do not need to be recreated or reloaded during the initialization process. [0002] NVM cells typically store information in a digital format. For example, NVM cells store information as 0 or 1. Thus, NVM cells typically transition between a first state and a second state that reflect the digital format. The states may include charge states (eg, flash memory) or magnetic states (eg, spin torque transfer magnetoresistive random access memory (STT-RAM)). [0003] Typically, an STT-MRAM cell includes a magnetic tunnel junction (MTJ) that acts as a storage structure for a bit of info...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/08G11C16/02H10N50/10
CPCG11C11/161G11C11/1659G11C11/1675H10B61/22H10N50/10
Inventor A.奈伊
Owner INFINEON TECH AG
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