X digital subscriber line (xDSL) data transmission device and method

Abstract

An x digital subscriber line (xDSL) data transmission device is disclosed in the present invention. xDSL chipsets and a first chip are set in a line card. A traffic management chip and a second chip are set in a main control board. The first chip is connected to the xDSL chipsets via a Universal Test & Operation PHY Interface for Asynchronous Transfer Mode (UTOPLA) or Packer over Sonet PHY (POSPHY) bus, and is connected to a backplane via an SERDES bus. The second chip is connected to the traffic management chip via an UTOPLA or POSPHY bus, and is connected to the backplane via an SERDES bus. The first chip and the second chip perform data conversion between the UTOPLA or POSPHY bus and the SERDES bus in an uplink and a downlink direction. The present invention also discloses an xDSL data transmission method, realizing xDSL data transmission with low cost and high performance.

Description

technical field [0001] The present invention relates to a Digital Subscriber Line (xDSL, Digital Subscriber Line) access technology in the communication field, in particular to an xDSL data transmission device and method. Background technique [0002] At present, the broadband access network based on xDSL has fundamentally realized the broadbandization of the "last mile". With the development of multimedia services and the improvement of broadband speed requirements, it is urgent to realize a broadband access of up to 8M or more on xDSL. Asymmetric Digital Subscriber Line (ADSL2+, Asymmetric Digital Subscriber Line2Plus) access technology can provide up to 20M access bandwidth within 1 km, very high-speed digital subscriber loop (VDSL2, Very High Digital Subscriber Line2) can even provide up to 500 meters within 500 meters Provide up to 50M access bandwidth, but the premise is to ensure that the xDSL central office access equipment is as close as possible to the user. [0...

AI Technical Summary

Problems solved by technology

The advantage of the first hardware implementation method is that the main control board and the backplane are simple to implement, and the throughput of the whole frame supported by it is relatively large, and the backplane is usually not a performance bottleneck; the disadvantage is that the hardware cost is high, and the chip placed on the line card single board Too many are not convenient for the size reduction of the chassis, and the heat dissipation requirements of the line cards are relatively high

The advantage of the second hardware implementation method is that the hardware cost is lower, the chips of the main control board and the line card are placed more evenly, and the chassis can be designed to be smaller or support more xDSL users; the disadvantage is that the backplane design is more complicated, Since the UTOPIA bus or POSPHY bus is directly passed through the backplane, the bus rate is likely to be low, and it is difficult for the bus to support a clock rate above 50MHz, which is likely to become the throughput bottleneck of the entire system.

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