All-NMOS 4-transistor non-volatile memory cell

Abstract

A method of programming a non-volatile memory (NVM) cell array that includes a plurality of all-NMOS 4-transistor NVM cells is provided. The gate electrodes of the four NMOS transistors in a cell are connected to a common storage node. In accordance with an embodiment of the programming method, the drain, bulk region and source and gate electrodes of a first NMOS programming transistor, a second NMOS read transistor, a third NMOS erase transistor and a fourth NMOS control transistor are all set to a positive reference voltage.; For each NVM cell in the array selected for programming, an inhibiting voltage is then applied to the source, drain and bulk region electrodes of the read transistor while maintaining the source and drain electrodes of the programming transistor at the positive reference voltage and the bulk region electrode of the programming transistor at either the positive reference voltage or at the inhibiting voltage. For each NVM cell in the array not selected for programming, the source, drain and bulk region electrodes of the read transistor and of the programming transistor are set to the inhibiting voltage.; For those cells in the array to be programmed, the interconnected source, drain and bulk region electrodes of the control transistor are ramped down from the positive reference voltage to a predefined negative control voltage for a preselected programming time while ramping down the interconnected source, drain and bulk region electrodes of the erase transistor from the positive supply voltage to a predefined negative erase voltage for the preselected programming time. For each cell to be programmed, at the end of the preselected time, the interconnected source, drain and bulk region electrodes of the control transistor are ramped up from the predefined negative control voltage to the supply voltage while ramping up the interconnected source, drain and bulk region electrodes of the erase transistor from the predefined negative erase voltage to the positive reference voltage.; For each NVM cell in the array, the source, drain, bulk region and gate electrodes of the programming, erase and control transistors are then returned to the positive reference voltage while the source, drain and bulk region electrodes of the read transistor are set to the inhibiting voltage.

Description

technical field [0001] The present invention relates to integrated circuit memory devices, and more particularly to an all NMOS four-transistor non-volatile memory (NVM) cell programmed using reverse Fowler-Nordheim tunneling . Background technique [0002] Commonly assigned U.S. Patent No. 7,164,606 issued Jan. 16, 2007 to Poplevine et al. discloses an all-PMOS four-transistor non-volatile memory (NVM) cell utilizing an inverted Fowler- Nordheim tunneling for programming. [0003] see figure 1 , as disclosed in U.S. Patent No. 7,164,606, according to the pair containing the floating gate electrode is commonly connected to the storage node P s A method for programming an NVM array of all PMOS four-transistor NVM cells 100, for each NVM cell to be programmed in the array, grounding all electrodes of the cell. Next, the inhibit voltage V n applied to the read transistor of the cell P r The body is connected to the source electrode V r , the erase transistor P of the cel...

AI Technical Summary

Problems solved by technology

However, four-transistor PMOS NVM cells cannot be used in certain integrated circuit fabrication processes where n-epitaxial silicon is grown shorting all N-wells together, or where each N-well is Needs to be surrounded by individual N+, P+, or trench guard rings, and charge will be lost if the floating poly gate crosses the guard rings

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