Multi-core multi-thread microprocessor-oriented virtual active page buffer method and device

Abstract

The invention discloses a multi-core multi-thread microprocessor-oriented virtual active page buffer method and device. The method comprises the following steps of: constructing a virtual active page buffer; managing construction, memory and deletion of a virtual active page in the virtual active page buffer according to an access memory request of an on-chip access memory component of a processor; and directly reading the virtual active page from the virtual active page buffer to improve the access memory performance when the access memory request is a read request and hit occurs in the virtual active page buffer. The device comprises a page predictor (1), an arbitrator (2), a virtual active page mark array (3), a virtual active page data array (4), a read-write queue (5), a command queue (6), a data return queue (7), a pending table (8) and a multi-path selector (9). According to the method and the device, the integral active page number of the memory can be increased, the cost for re-excitation after closing of the active page is reduced, and the access memory bandwidth is increased; and the method and the device have the advantages of high access memory performance and high extensibility.

Description

technical field [0001] The invention relates to the technical field of off-chip storage bandwidth optimization in the architecture design of multi-core multi-thread microprocessors, in particular to a method for virtual active page buffering for multi-core multi-thread microprocessors when the number of processor threads is large and devices. Background technique [0002] The mainstream off-chip memory uses DDR2 and DDR3 memory (hereinafter collectively referred to as DDR), which are all based on SDRAM. DDR SDRAM is a four-dimensional storage structure indexed by rank, bank, row and column. The memory controller generally transmits memory access instructions to SDRAM in the order of first-in-first-out. This method of scheduling according to program order is simple to implement, but due to memory bank competition, continuous access to the same memory bank must wait for the previous access to complete. Memory bandwidth utilization is low. [0003] The active page in the SDR...

AI Technical Summary

Problems solved by technology

[0005] Break through the bottleneck of traditional off-chip storage bandwidth optimization methods in multi-core multi-thread processors, and solve the problem of frequent opening and closing of active pages in SDRAM caused by the small correlation of address flows between threads in multi-core multi-thread processors. The problem of limited actual effective bandwidth optimization space

For multi-core multi-thread processors, the correlation between address streams is small. When the number of thread

Images