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Semiconductor processing equipment and method of use thereof

A technology for processing equipment and semiconductors, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of reducing the effect of processing, wafer scratches, wafer contamination, etc., to reduce the area of ​​scratches, The effect of reducing the contact area and avoiding scratches

Inactive Publication Date: 2016-03-30
SUNOVEL SUZHOU TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] 1) Since only one end of the wafer and the wafer cover is inserted into the groove of the processing container for fixing, and the other end does not take any fixing measures, during the processing, the gas in the processing container cavity will pass through all The gap between the wafer and the wafer cover is separated from the wafer and the wafer cover, thereby causing contamination of the surface of the wafer that does not need to be processed;
[0005] 2) Since the surface of the wafer is in complete contact with the entire surface of the wafer cover, the friction between the two will cause a large area of ​​scratches on the surface of the wafer; in addition, when the wafer is subjected to high temperature treatment When (such as annealing), the surface of the wafer and the wafer cover is prone to sticking;
[0006] 3) The width of the groove of the processing container is usually the same as or close to the sum of the thickness of the wafer cover and the wafer, so as to effectively keep the vertical state of the wafer during processing. Therefore, when the wafer cover and the wafer are placed During the process of inserting the wafer into the groove of the processing container, the wafer and the inner wall of the groove will also rub against each other, thereby scratching the surface of the wafer;
[0007] 4) Since the size of the groove of the processing container is usually fixed, it cannot flexibly meet the requirements for processing wafers of different thicknesses;
[0008] 5) Since the groove of the processing container is partially attached to the side of the wafer that needs to be processed, the exposed side of the wafer is partially blocked, which reduces the effect of processing and reduces the effective use area of ​​the wafer

Method used

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  • Semiconductor processing equipment and method of use thereof
  • Semiconductor processing equipment and method of use thereof
  • Semiconductor processing equipment and method of use thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0053] Please refer to Figure 1(a) to Figure 1(c) , wherein, Fig. 1(a), Fig. 1(b) and Fig. 1(c) are respectively a schematic perspective view, a schematic top view and a schematic cross-sectional view along section line AA' of a wafer cover according to a preferred embodiment of the present invention.

[0054] As shown in the figure, the wafer cover 100 includes a bottom surface and a side wall connected to the bottom surface and surrounding the bottom surface, and a space between the side wall and the bottom surface forms a groove 101 . Wherein, the shape of the wafer cover 100 (that is, the shape of the bottom surface) is preferably circular, which is the same as the shape of the wafer, so that after the wafer cover 100 and the wafer are bonded together, the wafer can be completely covered. One surface of the circle only exposes the other surface, which is convenient for single-sided treatment of the exposed surface. In addition, the process of forming a circular wafer cov...

Embodiment 2

[0058] On the basis of referring to the description of the same part in the first embodiment, please refer to Figure 2(a) to Figure 2(c) , wherein, FIG. 2(a), FIG. 2(b) and FIG. 2(c) are respectively a schematic perspective view, a schematic top view and a schematic cross-sectional view along the section line AA' of a wafer cover according to another preferred embodiment of the present invention. The difference from the wafer cover shown in the first embodiment above is that, as shown in the figure, in this embodiment, the side wall and the bottom surface of the wafer cover 100 form two grooves, and the two grooves They are respectively located on both sides of the bottom surface. As shown in the figure, the two grooves are respectively a groove 102 and a groove 103 . The depth of the groove 102 (as shown in H in Fig. 2(c) 3 shown) and the depth of the groove 103 (as shown in Figure 2(c) H 4 shown) is preferably the same, and the depth ranges from 5 μm to (H 1 -200) / 2μm. ...

Embodiment 3

[0061] On the basis of referring to the description of the same part in the first embodiment, please refer to image 3 , image 3 It is a schematic cross-sectional view of a wafer cover according to another preferred embodiment of the present invention. The difference from the wafer cover shown in the first embodiment above is that, as image 3 As shown in the position circled by the dotted line, in this embodiment, the upper surface of the sidewall surrounding the groove 101 in the wafer cover 100 (that is, the area in contact with the wafer) is a rough structure (such as a suede structure) Wait). If the area where the wafer cover 100 is in contact with the wafer is smooth, and the surface of the wafer to be processed is usually smooth, then in the process of processing, due to the effect of high temperature (such as high temperature annealing), the wafer The area where the dome cover 100 is in contact with the wafer is prone to sticking, which makes it difficult to separa...

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Abstract

The invention provides an application method of a semiconductor processing device. The application method includes the steps of attaching a wafer and a wafer cap to form a first cavity between the wafer and the wafer cap; vertically embedding the wafer and the wafer cap into a first groove at the inner bottom of a processing vessel cavity; clamping the wafer and the wafer cap from above by a counterweight; and processing the wafer. Correspondingly, the invention further provides the wafer cap, a processing vessel, the counterweight, and the semiconductor processing device. Separation between the wafer and the wafer cap in processing can be prevented effectively, the area of contact between the wafer, the wafer cap and the processing vessel can be decreased effectively, and the semiconductor processing device is applicable to wafers different in thickness and is of certain flexibility.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor processing device and a method for using the same. Background technique [0002] In semiconductor manufacturing, it is often necessary to perform single-sided processing on the wafer, such as performing single-sided diffusion, ion implantation, evaporation, sputtering, deposition or annealing operations on the wafer. The semiconductor processing equipment used to perform the above operations generally includes a processing container 500 and a wafer cover 600, please refer to Figure 9 , Figure 9 It is a schematic cross-sectional view of semiconductor processing equipment in the prior art during use. Wherein, there is generally a rectangular groove 503 at the bottom of the processing container chamber 501, and the groove 503 is used to fix the wafer 700 and keep the wafer 700 in a vertical state. The wafer cover 600 is usually a piece of wafer. After bo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/687H01L21/67
Inventor 朱慧珑尹海洲骆志炯
Owner SUNOVEL SUZHOU TECH