Bit line structure and manufacturing method thereof
A manufacturing method and bit line technology, applied in semiconductor/solid-state device manufacturing, electrical components, transistors, etc., can solve problems such as the inability to apply semiconductor technology and the inability to solve the floating body effect
Active Publication Date: 2015-02-11
WINBOND ELECTRONICS CORP
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Problems solved by technology
However, this method can only partially improve the bit line-bit line parasitic capacitance, and cannot solve the floating body effect, and cannot be applied to more advanced semiconductor processes
Method used
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Embodiment Construction
[0028] See figure 1 , which is a top view of a DRAM provided by an embodiment of the present invention. In a semiconductor substrate 100, a plurality of bit line trenches and a plurality of word line trenches are substantially arranged vertically and alternately. Each bit line trench contains a bit line 102, each word line trench contains a word line 104, and the word line 104 is divided into two left and right (such as figure 1 shown). The active region 106 of the transistor is an unrecessed region, thus forming a pillar. Each bit line 102 and word line 104 is electrically connected to the active area of the transistor, and each provides input / output signals through plugs 108 , 110 connected to external circuits. According to the embodiment of the present invention, the width of each bit line and word line and the area they enclose are determined according to the minimum element size F, so as to achieve high-density stacking. Therefore, the dynamic random access memory ...
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The invention provides a bit line structure which comprises a semiconductor base provided with a bottle groove inside. The bottle groove comprises a first groove, an enlarged second groove, a first insulating layer, a second insulating layer, a metal wire and a bit line contact member. Each of the first and second grooves is provided with a first side wall and a second side wall, which are opposite to each other. The first insulating layer is lined in the bottle groove. The second insulating layer covers the first insulating layer in the second groove, the first side walls are provided with exposed parts which are not covered by the first and second insulating layers, the first insulating layer on the first side walls is provided with an exposed part which is not covered by the second insulating layer, and the exposed parts of the first side walls are close to the bottom of the first groove and is disposed between the bottom of the first groove and the exposed part of the first insulating layer. The metal wire is located in the second insulating layer. The bit line contact member is located on the metal wire.
Description
technical field [0001] The present invention relates to semiconductor devices, and more particularly to a dynamic random access memory and a manufacturing method thereof. Background technique [0002] Currently, in a stacked dynamic random access memory (Dynamic Random Access Memory, hereinafter referred to as DRAM), the active region of the transistor is formed in a single crystal semiconductor substrate. The capacitor is disposed on the top of the active area. The bit lines and word lines are buried in the semiconductor substrate, and each bit line and word line are electrically connected with the active area of the transistor, and the change of charge in the storage capacitor is controlled by the bit line and the word line. [0003] However, the buried bit line (BL) of the stacked DRAM will become more and more serious due to the shrinking process size of the buried bit line (BL-BL capacitance) between different buried bit lines. In addition, in the stacked DRAM, a fl...
Claims
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IPC IPC(8): H01L21/8242H01L27/108
Inventor 郭泽绵
Owner WINBOND ELECTRONICS CORP