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A Recognizable Chip and Method for Adding Graphics

A technology of adding graphics and chips, which is applied in special data processing applications, instruments, electrical digital data processing, etc., and can solve the problems of not being able to recognize chips and adding graphics analysis tools

Active Publication Date: 2015-08-19
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The present invention provides an identifiable chip and a method for adding graphics thereof, which mainly solves the problems of the layout design of the existing chip and the inability to identify newly added graphics in different versions of the chip or the need to use special analysis tools in the final manufactured chip

Method used

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  • A Recognizable Chip and Method for Adding Graphics
  • A Recognizable Chip and Method for Adding Graphics
  • A Recognizable Chip and Method for Adding Graphics

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0026] Under the premise that cost and time are usually considered in the design and production of chips, most of the improvement and optimization of chips are the changes of metal interconnection (back-end process). The following examples use metal interconnects in chip manufacturing as an example. (This is just a special case, the newly added layer can be all the layers in the chip design and production, not limited to the layers in the subsequent process)

[0027] All layers used in the layout design are available in the layer selection window (e.g. figure 1 (Add) to select and use, only the layers to be used in the example are shown here.

[0028] The specific example of adding graphics is as follows:

[0029] Such as figure 1 As shown in the figure, on the basis of the original layer selection window, a new layer that is only used for adding graphics to the layout is added. In MX, X=0, 1, 2..., respectively represent metal 0 layer, metal 1 layer, metal 2 layer... MX ...

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PUM

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Abstract

The invention provides an identifiable chip and a method for adding graphs for the same. The identifiable chip and the method mainly solve the problem that graphs newly added in different versions of chips cannot be identified or special analysis tools are required to identify the newly added graphs during layout design for the chips and the finally manufactured chips at present. The method for adding the graphs for the identifiable chip includes creating metal layers of layouts of an original version of the chip; and adding the graphs for the various layouts, and the like. The identifiable chip comprises a plurality of resistors, and the metal wire layers among the resistors are different from one another. The identifiable chip and the method have the advantages that only the layers used for adding the graphs need to be added into a layout design for the chip, layouts of a new version and the chip are obtained via the layers, and the newly added graphs in the layouts of the new version can be easily and directly identified without special analysis tools.

Description

technical field [0001] The invention relates to an identifiable chip and a method for adding graphics thereof, belonging to the field of chip design. Background technique [0002] Chips are manufactured by fabs by using different masks one by one to carry out photolithography, oxidation, ion implantation, etching and other processes on silicon wafers. It is mainly divided into front-end process and back-end process. The front-end process is mainly to make devices, and the back-end process is to interconnect metal wires. [0003] The mask plate used to manufacture the chip is made according to the layout data file provided by the chip layout designer. Chip layout designers need a series of design files provided by the fab when designing the layout. In these documents, the fab will provide different layers for chip layout design according to its own process conditions. The layout designer uses these layers for layout design and finally obtains the chip layout. [0004] Amo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 李晓骏
Owner XI AN UNIIC SEMICON CO LTD