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A method for recognizing chip deletion pattern

A chip and graphics technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problem of not being able to identify the chip, newly deleted graphics, etc.

Active Publication Date: 2016-01-13
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The present invention provides a method for identifying and deleting graphics on a chip, which mainly solves the problems of the layout design of the existing chip and the inability to identify newly deleted graphics in different versions of the chip or the need to use special analysis tools in the final manufactured chip

Method used

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  • A method for recognizing chip deletion pattern
  • A method for recognizing chip deletion pattern
  • A method for recognizing chip deletion pattern

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0023] Under the premise that cost and time are usually considered in the design and production of chips, most of the improvement and optimization of chips are the changes of metal interconnection (back-end process). The following examples use metal interconnects in chip manufacturing as an example. (This is just a special case, the newly added layer can be all the layers in the chip design and production, not limited to the layers in the subsequent process)

[0024] All layers used in the layout design are available in the layer selection window. Such as figure 1 (Delete) to select and use, only the layers to be used in the example are shown here.

[0025] The specific examples of deleting graphics are as follows:

[0026] In the original design of a certain chip, the circuit schematic diagram of a current mirror structure is as follows Figure 2a as shown, Figure 3a for the corresponding layout. After testing the original chip, it is found that this current mirror str...

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PUM

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Abstract

The invention provides a method capable of identifying a graph deleted by a chip and mainly solves the problems that in a layout design of a conventional chip and a finally-manufactured chip, newly-deleted graphs in different versions of chips cannot be identified or a special analysis tool needs to be used. The method capable of identifying the graph deleted by the chip comprises the following steps of establishing a metal layer of a chip original version layout; and carrying out various versions of deleting and the like. According to the method disclosed by the invention, layers used for deleting the graph are additionally added. New versions of layouts and chips, which are obtained by using the layers, are used and the special analysis tool is not needed, so that newly-deleted graphs can be easily and directly identified from the new versions of the layouts.

Description

technical field [0001] The invention relates to a method for deleting graphics on a chip, which belongs to the field of chip design. Background technique [0002] Chips are manufactured by fabs by using different masks one by one to carry out photolithography, oxidation, ion implantation, etching and other processes on silicon wafers. It is mainly divided into front-end process and back-end process. The front-end process is mainly to make devices, and the back-end process is to interconnect metal wires. [0003] The mask plate used to manufacture the chip is made according to the layout data file provided by the chip layout designer. Chip layout designers need a series of design files provided by the fab when designing the layout. In these documents, the fab will provide different layers for chip layout design according to its own process conditions. The layout designer uses these layers for layout design and finally obtains the chip layout. [0004] Among the layers use...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 李晓骏
Owner XI AN UNIIC SEMICON CO LTD