Unlock instant, AI-driven research and patent intelligence for your innovation.
Semiconductor memory test method and semiconductor memory
What is Al technical title?
Al technical title is built by PatSnap Al team. It summarizes the technical point description of the patent document.
A memory test and semiconductor technology, applied in static memory, read-only memory, information storage, etc., can solve the problems of reduced reliability of semiconductor memory and undetectable memory cells
Inactive Publication Date: 2016-05-04
SOCIONEXT INC
View PDF4 Cites 1 Cited by
Summary
Abstract
Description
Claims
Application Information
AI Technical Summary
This helps you quickly interpret patents by identifying the three key elements:
Problems solved by technology
Method used
Benefits of technology
Problems solved by technology
In this case, the original bad memory cell cannot be detected, and the reliability of the semiconductor memory is reduced
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more
Image
Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
Click on the blue label to locate the original text in one second.
Reading with bidirectional positioning of images and text.
Smart Image
Examples
Experimental program
Comparison scheme
Effect test
no. 1 example ）
[0027] figure 1 is an example of the semiconductor memory testing method according to the first embodiment.
[0028] also, figure 2 is an example of the semiconductor memory according to the first embodiment. will first describe figure 2 .
[0029] The semiconductor memory 1 is, for example, a nonvolatile memory such as a flash memory, and includes a memory core 2, a command generation circuit 3, a test control circuit 4, an operation control circuit 5, an address controller 6, an address generation circuit 7, and data input and output Circuit 8.
[0030] The memory core 2 includes a memory cell array 2a, a reference cell array 2b, a selection circuit 2c, and a read / write circuit 2d.
[0031] A plurality of memory cells are arranged in a matrix in the memory cell array 2a. The reference cell array 2 b includes reference cells to be compared with memory cells (hereinafter simply referred to as “cells”) included in the memory cell array 2 a at the time of testing. For e...
no. 2 example ）
[0059] image 3 is an example of the semiconductor memory according to the second embodiment.
[0060] The semiconductor memory 10 according to the second embodiment is, for example, a flash memory. The semiconductor memory 10 includes a memory core 11 , a command generation circuit 12 , a built-in self-test (BIST) control circuit 13 , an operation control circuit 14 , an address controller 15 , an address generation circuit 16 , and a data input-output circuit 17 . In addition, the semiconductor memory 10 includes an internal voltage generation circuit 18 , a redundant content addressable memory (CAM) 19 , a CAM access control circuit 20 , and a bus control circuit 21 .
[0061] The memory core 11 includes a memory cell array 111 , a reference cell array 112 , an X control circuit 113 , a Y control circuit 114 , a read-write amplifier 115 and a redundancy circuit 116 .
[0062] A plurality of cells are arranged in a matrix in the memory cell array 111 . The memory cell arr...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More
PUM
Login to View More
Abstract
A semiconductor memory testing method and a semiconductor memory are disclosed. The first erase test is performed by applying an erase pulse to memory cell series included in the memory cell array and divided into a plurality of groups until a group for which erasure completion determination is made occurs. A second erase test is performed on the other series of memory cells including the series of memory cells based on the number of erase pulses when the group first determined to be erase complete is detected.
Description
technical field [0001] Embodiments discussed herein relate to a semiconductor memory testing method and a semiconductor memory. Background technique [0002] The following sample erase test is proposed as a semiconductor memory erase test. In this sample erase test, the number of erase pulses used to complete erasure of a portion of memory cells in a memory cell array is found, and erasure is performed in the remaining area based on the number of erase pulses. [0003] The following erasure test method is proposed as an EEPROM erasure test method. In this erasing test method, an erasing test is repeated in a part of the storage area until it is determined that erasing is normally performed, the width of an erasing pulse is set based on the number of repetitions, and Erase tests are performed on most of the storage areas. [0004] Japanese Laid-Open Patent Publication No. 08-31189 [0005] Japanese Patent Laid-Open No. 2000-207897 [0006] Japanese Laid-Open Patent Publi...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More
Application Information
Patent Timeline
Application Date:The date an application was filed.
Publication Date:The date a patent or application was officially published.
First Publication Date:The earliest publication date of a patent with the same application number.
Issue Date:Publication date of the patent grant document.
PCT Entry Date:The Entry date of PCT National Phase.
Estimated Expiry Date:The statutory expiry date of a patent right according to the Patent Law, and it is the longest term of protection that the patent right can achieve without the termination of the patent right due to other reasons(Term extension factor has been taken into account ).
Invalid Date:Actual expiry date is based on effective date or publication date of legal transaction data of invalid patent.
Login to View More 
Login to View More