vertical channel transistor

Abstract

The invention discloses a vertical channel transistor, comprising a substrate comprising at least one pair of first and second grooves which are oppositively arranged; an embedded bit line arranged on the bottom of the first groove; a first source / drain region electrically connected to the embedded bit line; a second source / drain region adjacent to the top of the first groove; an insulated grid wire embedded to the bottom of the second groove; an epitaxial layer arranged in the second groove and adjacent to the insulated grid wire; a diffusion region arranged relative to the epitaxial layer, wherein a first insulating layer is arranged between the epitaxial layer and the diffusion region; a front grid located on a first side surface of the substrate and a rear grid located on a second side surface of the substrate relative to the first side surface.

Description

technical field [0001] The present invention relates to a semiconductor device, and more particularly to a vertical channel, double-gate Fin Field Effect Transistor (FinFET) with buried bit lines. Background technique [0002] Vertical FinFETs with buried bit lines are gradually becoming the next 4F due to their streamlined mid-range process (MOL) 2 The mainstream of the generation (F represents the minimum line width of lithography technology). However, at the same time, its front-end process (FEOL) is increasingly complex. For example, at the 30nm generation, shallow trench isolation (STI) regions with half-size and STI aspect ratios higher than 20 are required. It can be seen that the trenches to be filled with the oxide layer will become a major obstacle to reducing the size of the DRAM. [0003] Vertical surrounding gate transistors (SGT) with buried bit lines, which use increased isolation rules to greatly reduce the difficulty of shallow trench isolation manufactur...

AI Technical Summary

Problems solved by technology

For example, parasitic bipolar transistors driven by floating body effects can cause instability in array threshold voltages during cell operation

In addition, the transition carriers generated at the junction of the bit line and the bulk accumulation due to impact ionization will also reduce the threshold voltage of the transistor.

Delay becomes worse as leakage current increases

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