A method for forming a hard mask layer

Abstract

The invention discloses a method for forming a hard mask layer. The method comprises the following steps: a substrate is provided, wherein a sacrificial layer with a pattern is formed on the substrate in advance; first hard mask material layers are formed on the surface of the substrate and the surface and side walls of the sacrificial layer; etchback is conducted so as to form gap walls on the side walls of the sacrificial layer, wherein the gap walls are formed by the first hard mask material layers; the sacrificial layer is removed; second hard mask material layers are formed on the surface of the substrate and the surfaces of the gap walls. The method for forming the hard mask layer solves the problems caused by the adoption of a PR mask or a hard mask with a circular arc-shaped top portion, thereby being capable of realizing good LWR and CD homogeneity; besides, the method for forming the hard mask layer is compatible with a traditional process, thereby being capable of lowering cost.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for forming a hard mask layer. In addition, the present invention also relates to a method for performing Self-Aligned Double Patterning (SADP, Self-Aligned Double Patterning) using the hard mask layer. Background technique [0002] As the size of semiconductor devices continues to shrink, the critical dimension (CD) of lithography is gradually approaching or even exceeding the physical limit of optical lithography, which poses more severe challenges to semiconductor manufacturing technology, especially lithography technology. The double patterning technology also arrived at the right time. The basic idea is to form the final target pattern through two patterns, so as to obtain the limit of lithography that cannot be achieved by single patterning. [0003] Double patterning technology currently mainly includes the following three types: SADP (self...

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Problems solved by technology

[0008] However, despite the many advantages of this technique, due to the full etch-back process used to form the spacer, the top of the resulting spacer is arc-shaped, such as figure 1 shown

Patterning the target material layer with such a hard mask layer with a rounded top results in poor pattern height uniformity in the patterned target material layer, resulting in poor linewidth roughness (LWR) and CD uniformity. are poor, which in turn leads to a decrease in the performance of the final semiconductor device

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