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A method for forming a hard mask layer

A hard mask layer and hard mask technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as poor height uniformity, poor line width roughness CD uniformity, and reduced semiconductor device performance. Reduce manufacturing cost, realize online process control, and the effect of reliable online process control

Active Publication Date: 2016-04-06
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] However, despite the many advantages of this technique, due to the full etch-back process used to form the spacer, the top of the resulting spacer is arc-shaped, such as figure 1 shown
Patterning the target material layer with such a hard mask layer with a rounded top results in poor pattern height uniformity in the patterned target material layer, resulting in poor linewidth roughness (LWR) and CD uniformity. are poor, which in turn leads to a decrease in the performance of the final semiconductor device

Method used

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  • A method for forming a hard mask layer
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  • A method for forming a hard mask layer

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no. 1 example

[0041] Below, will refer to Figures 2A-2F as well as image 3 A method for forming a hard mask layer in a semiconductor manufacturing process according to a first embodiment of the present invention will be described in detail.

[0042] refer to Figures 2A-2F , which shows a schematic cross-sectional view of each step in the method for forming a hard mask layer according to the first embodiment of the present invention.

[0043] First, a substrate 210 is provided. Such as Figure 2A As shown, a target material layer 220 is pre-formed on a substrate 210 , and a sacrificial layer 230 having a pattern is pre-formed on the target material layer 220 .

[0044] The constituent material of the substrate 210 may be undoped single crystal silicon, single crystal silicon doped with N-type or P-type impurities, polycrystalline silicon, silicon germanium, or silicon-on-insulator (SOI) and the like.

[0045] The target material layer 220 may be an interconnect wiring layer, an inter...

no. 2 example

[0061] Below, will refer to image 3 A method for forming a hard mask layer in a semiconductor manufacturing process according to a second embodiment of the present invention will now be described. image 3 Shown in the second embodiment of the present invention is equivalent to the first embodiment Figure 2E A schematic cross-sectional view of the . The difference between the second embodiment and the first embodiment is that the constituent material of the first hard mask material layer 340a is not limited to silicon, but may also include SiO 2 At least one of , SiN, TaN and TiN; in addition, the second hard mask material layer 340b is made of silicon germanium, which is formed by a self-formation method such as lateral epitaxial growth, and after forming this layer of silicon germanium hard mask There is no need to perform etch back after the film layer. Apart from that, the specific process steps and various parameters involved in the second embodiment are the same as ...

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Abstract

The invention discloses a method for forming a hard mask layer. The method comprises the following steps: a substrate is provided, wherein a sacrificial layer with a pattern is formed on the substrate in advance; first hard mask material layers are formed on the surface of the substrate and the surface and side walls of the sacrificial layer; etchback is conducted so as to form gap walls on the side walls of the sacrificial layer, wherein the gap walls are formed by the first hard mask material layers; the sacrificial layer is removed; second hard mask material layers are formed on the surface of the substrate and the surfaces of the gap walls. The method for forming the hard mask layer solves the problems caused by the adoption of a PR mask or a hard mask with a circular arc-shaped top portion, thereby being capable of realizing good LWR and CD homogeneity; besides, the method for forming the hard mask layer is compatible with a traditional process, thereby being capable of lowering cost.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for forming a hard mask layer. In addition, the present invention also relates to a method for performing Self-Aligned Double Patterning (SADP, Self-Aligned Double Patterning) using the hard mask layer. Background technique [0002] As the size of semiconductor devices continues to shrink, the critical dimension (CD) of lithography is gradually approaching or even exceeding the physical limit of optical lithography, which poses more severe challenges to semiconductor manufacturing technology, especially lithography technology. The double patterning technology also arrived at the right time. The basic idea is to form the final target pattern through two patterns, so as to obtain the limit of lithography that cannot be achieved by single patterning. [0003] Double patterning technology currently mainly includes the following three types: SADP (self...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/033
Inventor 王新鹏
Owner SEMICON MFG INT (SHANGHAI) CORP
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