A Design Method of XDP Based on NUMA Computer Architecture

Abstract

The present invention provides a kind of XDP design method based on NUMA computer system structure, sets a global controller realized by FPGA / CPLD or BMC / SMC, the main function of this global controller controls the switching of MUX and SW, thereby realizes XDP chain The dynamic and intelligent configuration of the link, and the intelligent adaptation of the link matching impedance can also be realized by controlling the MUX; in addition, the global controller can also control the SW to realize the bypass of any CPU, which is convenient for fault location. Compared with the prior art, the XDP design method based on the NUMA computer architecture ensures the maximum flexibility of the XDP link; saves costs, can reduce the cost of debugging fixtures by more than 50%, has strong practicability, and is easy to popularize.

Description

technical field [0001] The invention relates to the technical field of computer applications, in particular to an XDP design method based on NUMA computer architecture. Background technique [0002] In order to facilitate debugging and testing, all major semiconductor manufacturers will configure a debugging interface for the chip. The JTAG interface is widely used by major manufacturers because of its simple design, which allows multiple devices to be connected in series to form a JTAG chain, and each device is individually debugged and tested. [0003] The JTAG interface of Intel CPU is called ITP interface (In Target Probe). With the enhancement of debugging complexity, Intel has extended this interface to XDP (eXtend Debug Port) interface on the basis of ITP. Through the XDP interface, you can observe Memory, setting breakpoints, receiving various events of the CPU, etc., the integration of chips is getting higher and higher, and debugging is becoming more and more compl...

AI Technical Summary

Problems solved by technology

[0008] Using this design method can meet the requirements of XDP debugging and testing, but when debugging in multi-partition state, multiple XDP debuggers are required, and XDP synchronization cables are required for connection; it not only increases the cost of debugging and testing hardware, but also requires In this state, due to the complex system architecture and cumbersome structural design, in many cases, the wiring of XDP synchronization cables is very difficult; due to the need for redundant hardware overhead, the reliability of the design is also poor

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