Debugging device and debugging method
A technology for resetting signals and information codes, applied in the direction of responding to errors, redundant codes for error detection, and using power-on tests to detect faulty hardware. Knowledge of Port80 code information and other issues to achieve the effect of reducing debugging time and improving debugging efficiency
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[0028] Please refer to figure 1 As shown, it is a schematic diagram of the server of the present invention. The server 100 includes a central processing unit (Central Processing unit, CPU) 102, a memory (Dual In-line Memory Module, DIMM) 104, a basic input output system (Basic Input Output System, BIOS) memory 106, a control chip 108 and the present invention Debugger 1 10. The central processing unit 102 is coupled to the memory 104 . The BIOS memory 106 is used for storing the BIOS. The control chip 108 is coupled to the CPU 102 and the BIOS unit 106 .
[0029] Moreover, the control chip 108 is coupled to the central processing unit 102 through, for example, a direct media interface (Direct Media Interface, DMI) bus. The control chip 108 is coupled to the BIOS memory 106 through, for example, a Serial Peripheral Interface (SPI) bus. Wherein, the central processing unit 102 , the memory 104 and the BIOS memory 106 are not the focus of the present invention, so they will ...
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