Resettable scan-structured flip-flops resistant to single-event upsets and single-event transients
A single-event transient, anti-single-event technology, applied in pulse generation, electrical components, generating electrical pulses, etc., can solve the problems of anti-single-event flip capability and low anti-single-event transient.
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[0039] figure 2 It is a schematic diagram of the logic structure of the anti-single event reversal and single event transient scanning structure D flip-flop of the present invention. The present invention consists of a clock circuit (such as image 3 shown), snubber circuits such as Figure 4 shown), scan control buffer circuit (such as Figure 5 shown), reset snubber circuit (as Figure 6 shown), the master latch (as Figure 7 shown), slave latches (as Figure 8 shown), the output buffer circuit (such as Figure 9 shown) composition. The anti-single-event reversal and anti-single-event transient resettable D flip-flop of the present invention has five input terminals and one output terminal. The five input terminals are clock signal input terminal CK, data signal input terminal D, scanning control signal input terminal SE, scanning data input terminal SI and reset signal input terminal RN; the output terminal is Q. The clock circuit receives CK, and outputs c1, c2 an...
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