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Package structure and assembly method thereof

A technology of packaging structure and chip set, which is applied in the direction of electrical components, electrical solid-state devices, circuits, etc.

Inactive Publication Date: 2017-05-10
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, interconnects across the common (i.e., top) chip are limited by corner crossing density
Additionally, power delivery to a common chip is also challenging because the direction of power transfer is vertically oriented along the vertical length of each of the multiple chips

Method used

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  • Package structure and assembly method thereof
  • Package structure and assembly method thereof
  • Package structure and assembly method thereof

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Embodiment Construction

[0022] In a chip stack like a 4Di chip stack, a large amount of silicon in the form of multiple chips arranged in parallel with a normal (top) chip is packaged and interconnected to provide an area multiplication of about 8.5X or more, with 57.6k connections for both power and communication between chip stacks and common chips. However, interconnection through the common chip is limited by corner crossing density and power delivery to the common chip presents challenges because power delivery is vertically oriented along the vertical length of each of the multiple chips.

[0023] According to embodiments described herein, there is provided a chip stack and embodied as a 4Di chip stack comprising groups arranged in at least active surface to active surface (i.e., face-to-face) with conductive elements disposed therebetween (such as small pitch microbumps or microconnections) of multiple chips. This provides a relatively high-bandwidth connection between pairs of chips (or, mor...

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Abstract

The present invention relates a packaging structure and a method of assembling a packaging structure. The packaging structure includes first and second chips, at least one surface of each of the first and second chips being an active surface and a common chip to which at least one of the first and second chips is electrically interconnected. The respective active surfaces of the first and second chips are directly electrically interconnected to one another in a face-to-face arrangement and are oriented transversely with respect to the common chip.

Description

technical field [0001] The present invention relates to packaging structures. More specifically, the present invention relates to packaging structures having direct electrical connections between the respective active surfaces of first and second chips and between at least one of the first and second chips and a common chip. Background technique [0002] As the size of complementary metal-oxide-semiconductor (CMOS) devices shrinks, chip packaging methods are investigated to improve system performance. In some cases, the stack of chips includes a plurality of chips arranged in parallel to form a module with a common chip disposed on one side of the module. The block is then connected to the circuit board along the side of the block opposite the common chip. [0003] In chip stacks that include a common chip and multiple chips arranged in side-by-side configurations, large amounts of silicon are packaged and interconnected. However, interconnects across a common (ie, top) c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/50H01L23/52H01L21/60H01L25/16
Inventor E·G·科尔根P·W·科特乌斯R·L·威斯涅夫
Owner GLOBALFOUNDRIES INC
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