A pulse clock generation logic with built-in level shifter and programmable rising edge and pulse width

Abstract

Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.

Description

technical field [0001] The disclosed embodiments generally relate to pulsed clock generation. More specifically, exemplary embodiments relate to generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. Background technique [0002] The increasing demand for extended battery life and high processing speed in the handheld device and mobile phone industries has created a corresponding demand for low power and efficient memory systems. To save power, the on-chip memory is limited to low supply voltage levels. [0003] However, conventional memory cells, such as 6-transistor static random access memory (6T-SRAM), cannot operate at extremely low voltages. A common solution involves the use of multiple voltage domains so that memory cells can operate at relatively higher voltage levels while other on-chip logic can operate at lower voltages. To implement multiple voltage domains, level shifters ar...

AI Technical Summary

Problems solved by technology

Conventional pulsed clock implementations are not well suited to meet these conflicting requirements for read and write operations on memory cells

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