RAM (Random Access Memory) output register processing method

A processing method and register technology, applied in information storage, static memory, digital memory information, etc.

Active Publication Date: 2015-02-11
锐立平芯微电子(广州)有限责任公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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  • RAM (Random Access Memory) output register processing method
  • RAM (Random Access Memory) output register processing method
  • RAM (Random Access Memory) output register processing method

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Embodiment Construction

[0020] Embodiments of the present invention are described in detail below.

[0021] Examples of the described embodiments are shown in the drawings, wherein like or similar reference numerals designate like or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention. The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and / or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in i...

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Abstract

The invention provides an RAM (Random Access Memory) output register processing method, which comprises the following steps: judging whether a register connected with RAM output exists or not; if the register connected with RAM output exists, judging whether the register needs to be compressed or not; if the register needs to be compressed, judging whether the register has an asynchronous setting control terminal or not; if the register has no asynchronous setting control terminal, correspondingly processing according to whether the register has asynchronous and synchronous zero clearing control terminals and a clock enable terminal or not. By classifying various register structures connected with the RAM output, the problem that RAM is realized in an FPGA (Field Programmable Gate Array) chip by using a proprietary macrocell RAMB of FPGA is solved, and the processing effect reaches a level equivalent to that of Synplify.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a method for processing RAM output registers in FPGA RTL synthesis. Background technique [0002] FPGA (Field-Programmable Gate Array), that is, field programmable gate array, is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gates. At present, the EDA development technology of FPGA (Field Programmable Gate Arrays) is mainly controlled by several major FPGA and EDA manufacturers, such as Xilinx, Altera, Synopsis, etc. The domestic technology development is still in the stage of following and imitating. Among them, RTL (Register-Transfer-Level) synthesis is an important part o...

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Application Information

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IPC IPC(8): G11C8/12
Inventor 李艳张东晓于芳
Owner 锐立平芯微电子(广州)有限责任公司
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