A hardware acceleration implementation device for backward training of convolutional neural network based on fpga

Abstract

The invention discloses a device for realizing hardware acceleration of backward training of convolutional neural network based on FPGA. This device is based on the basic processing modules of the backward training of each layer of the convolutional neural network, comprehensively considering the operation processing time and resource consumption, using methods such as parallel-serial conversion, data fragmentation, pipeline design resource reuse, etc., to achieve the largest possible Based on the principle of parallelism and as little resource consumption as possible, the backward training process of the Hcnn convolutional neural network is realized in the form of a parallel pipeline. The device makes full use of the characteristics of FPGA's data parallelism and pipeline parallelism, which is simple to implement, more regular in structure, more consistent in wiring, greatly increased in frequency, and has a remarkable acceleration effect. More importantly, this structure uses an optimized systolic array structure to balance IO reads and writes and calculations, improves throughput while consuming less storage bandwidth, and effectively solves the problem of convolution where data access speed is much faster than data processing speed. Problems with neural network FPGA implementation.

Description

technical field [0001] The present invention relates to one of the important development directions in artificial intelligence—the field of deep learning, and in particular to a hardware acceleration implementation device for backward training of convolutional neural network based on FPGA. Background technique [0002] In recent years, the field of artificial intelligence, especially machine learning, has achieved breakthrough achievements in both theory and application. Deep learning is one of the most important development directions of machine learning. Deep learning can learn features with multi-level abstraction. Therefore, deep learning has excellent performance in solving complex and abstract learning problems. However, as the problem continues to become more complex and abstract, the model of the deep learning network becomes more complex, and the learning time of the model also increases. For example, Google's "AlphaGo" uses a multi-layer neural network structure c...

AI Technical Summary

Problems solved by technology

Therefore, FPGA is a very good choice for deep learning acceleration. However, there are not many studies on the specific structure of FPGA implementation of deep learning algorithms. There are problems such as insufficient storage bandwidth, and there is still a lot of room for improvement in acceleration effects.

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