Method of packaging integrated circuits

Abstract

The present invention relates to methods of packaging integrated circuits. The technique of packaging integrated circuits involves attaching a chip to a conductive layer prior to forming a dielectric layer on an opposing surface of the conductive layer. Before the chips are arranged on the conductive layer, the conductive layer may first be formed on the carrier substrate. The chip can be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed prior to forming the dielectric layer. The dielectric layers may collectively form a coreless packaging substrate for an integrated circuit package.

Description

[0001] This application claims priority to US Patent Application No. 14 / 175,651, filed February 7, 2014, the entire contents of which are hereby incorporated by reference into this application. technical field Background technique [0002] Generally, integrated circuit (IC) chips are packaged to protect the chips from external contamination or physical damage. IC packages typically include, among other things, a substrate, a chip disposed on the substrate, and a heat sink disposed over the chip to dissipate heat from the IC package. Chips can be assembled on a substrate in a flip-chip configuration or a wire-bond configuration. [0003] In a flip-chip configuration, the chip is mounted on a substrate. When the chip is mounted on the substrate, it is "flipped" so that the solder bumps on the chip rest on corresponding contact pads on the substrate. In a wire bond configuration, the chip is electrically coupled to the substrate via bond wires. Signals from the integrated ci...

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Problems solved by technology

However, because coreless substrates are thinner and do not include a hard core layer, they are more susceptible to thermal deformation than substrates with a core layer

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