Optimization method for power consumption of three-value FPRM circuit by utilizing exhaustion method

Abstract

The invention discloses an optimization method for power consumption of a three-value FPRM (Fixed-Polarity Reed-Muller) circuit by utilizing an exhaustion method. The optimization method comprises the following steps: firstly, adopting a three-value FPRM logic function under p-polarity for expressing the three-value FPRM circuit; resolving a multiple-input operation contained in the three-value FPRM logic function, thereby acquiring a plurality of two-input model 3 adding gates and a plurality of two-input model 3 product gates under p-polarity; taking the power consumption caused by the two-input model 3 adding gates and two-input model 3 product gates as the power consumption of the three-value FPRM circuit under p-polarity, constructing and acquiring a power consumption estimation model of the three-value FPRM circuit; and lastly, utilizing the method of exhaustion to perform power consumption optimum polarity searching on the three-value FPRM circuit, thereby searching and acquiring the minimal power consumption and the optimal power consumption polarity of the three-value FPRM circuit. The optimization method has the advantages that the power consumption optimization for the three-value FPRM circuit is realized; 13 MCNC Benchmark circuits are randomly adopted for performing simulation verification; compared with 0 polarity, the optimum polarity searched according to the method provided by the invention has the advantages that the quantity of model 3 adding gates is averagely saved for 54.94%, the quantity of model 3 product gates is averagely saved for 46.89%, the power consumption is averagely saved for 72.7% and the effect of power consumption optimization is obvious.

Description

technical field [0001] The invention relates to a method for optimizing the power consumption of a ternary FPRM circuit, in particular to a method for optimizing the power consumption of a ternary FPRM circuit using an exhaustive method. Background technique [0002] With the continuous development of the scale and integration of integrated circuits, digital circuits will inevitably encounter problems such as power consumption, area and speed. Traditional digital circuits mostly use binary logic, but the low information content of binary signals has become the main factor restricting the development of integrated circuits. The multi-valued logic circuit increases the ability to carry information in a single line, which can effectively improve the utilization rate of space or time, reduce the connection of digital systems, and save circuit area and cost. The three-valued logic whose base is 3 has the smallest base in the algebraic system of multi-valued logic, which is easy ...

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Problems solved by technology

However, experts and scholars at home and abroad mainly focus on the polarity conversion technology of multi-valued RM logic circuits, and have not studied the power consumption optimization technology of multi-valued RM circuits.

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