Multi-threshold low-power-consumption optimization method based on number of critical paths and sensitivity

A technology of critical path and optimization method, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as high method complexity, unsatisfactory power consumption optimization effect, and weak priority index representation ability. Low method complexity, significant power optimization effect, and feature-rich effect

Pending Publication Date: 2021-04-16
JIANGNAN UNIV
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Problems solved by technology

[0008] In order to solve the problems existing in the existing multi-threshold low power consumption technology, such as weak characterization ability of priority indicators, high method complexity, and unsatisfactory power consumption optimization effect, the present invention provides a new unit replacement strategy based on a new unit replacement strategy. A multi-threshold low-power optimization method based on the number of critical paths and sensitivities, the method first replaces all low-threshold combinational logic units in the CMOS circuit to be optimized with high-threshold combinational logic units, and collects each combinational logic unit replacement Change information of timing and power consumption before and after, and then calculate the sensitivity of each combinational logic unit replacement according to these change information, and then record the number of critical paths passing through each combinational logic unit, and then according to the number of critical paths and Sensitivity evaluates the priority of the combinational logic unit in the replacement phase, and finally performs unit replacement for each combinational logic unit from high threshold to low threshold according to the priority until the CMOS circuit to be optimized just meets the timing constraint

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  • Multi-threshold low-power-consumption optimization method based on number of critical paths and sensitivity
  • Multi-threshold low-power-consumption optimization method based on number of critical paths and sensitivity
  • Multi-threshold low-power-consumption optimization method based on number of critical paths and sensitivity

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Embodiment 1

[0038] This embodiment provides a multi-threshold low-power optimization method based on the number of critical paths and sensitivities. The method first performs logic synthesis on the RTL design based on the low-threshold cell library and design constraint files, thereby obtaining the circuit netlist , power optimization is based on the circuit netlist.

[0039] After obtaining the circuit netlist, record the delay LD of each low-threshold combinational logic unit i and power dissipation LP i , and then replace all low-threshold combinational logic units with high-threshold combinational logic units, and record the delay HD of each high-threshold combinational logic unit i and Power Dissipation HP i , calculate the delay change ΔD of each combinational logic unit before and after the unit replacement operation i , power consumption variation ΔP i and sensitivity S i , where ΔD i =HD i -LD i , ΔP i = HP i -LP i , i = 1, 2, 3, . . .

[0040] Then record the numbe...

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Abstract

The invention discloses a multi-threshold low-power-consumption optimization method based on the number of critical paths and sensitivity, and belongs to the field of low-power-consumption design of integrated circuits. According to the method, the characteristics referred by the priority evaluation indexes are rich, the characterization capability of the priority is stronger, and compared with PCOM and GDSPOM methods, the method provided by the invention can simultaneously consider three factors, namely the delay variation before and after unit replacement, the power consumption variation and the number of key paths where the unit is located. According to the sorting result of the priorities, the method can preferentially execute unit replacement with higher income in the unit replacement process from the high threshold value to the low threshold value, and does not need to differentially treat a critical path and a non-critical path, so that the method is lower in complexity and easier to implement and apply, and the power consumption optimization effect of the method is remarkable.

Description

technical field [0001] The invention relates to a multi-threshold low-power optimization method based on the number of critical paths and sensitivity, and belongs to the field of integrated circuit low-power design. Background technique [0002] With the development of CMOS technology to the deep submicron stage, the proportion of leakage power consumption will gradually increase with the progress of the process, and leakage power consumption has become one of the important considerations in low power consumption design. [0003] Multi-threshold technology (also known as multi-threshold CMOS technology) is an effective method to reduce static power consumption of CMOS circuits. In order to solve the compromise problem of performance and power consumption, CMOS process manufacturers have introduced a variety of standard cell libraries with different threshold voltages: HVT library, RVT (some manufacturers call it MVT or SVT) library and LVT library, which are called high Thr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/327G06F30/3312
Inventor 虞致国常龙鑫顾晓峰
Owner JIANGNAN UNIV
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