Digital delay implementation method for integrated circuit and circuit

Abstract

The invention provides a digital delay implementation method for an integrated circuit and a circuit. The invention can achieve long delay for a duration of nxTperiod, where Tperiod is an input clock period and n is an arbitrary natural number; and also greatly reduce the number of bits of an adder, reduce the combinatorial logic area, and shorten the logic delay. The method comprises the steps of 1) determining the total amount of delay M based on delay time Tdelay and a clock period Tperiod, and converting M from a decimal format into a binary code bN-1...bj...b1b0; 2) determining a counting target U: adding the coefficients before bj=1 in the binary code bN-1...bj...b1b0 converted from M to obtain the counting target U, and converting U from a decimal format into a binary code bP-1...bi...b1b0; and 3) based on the obtained counting target, performing frequency division by counting variation in step length and then achieving the delay for a duration of nxTperiod by direct counting, where Tperiod is the input clock period and n is an arbitrary natural number.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a digital delay realization method and circuit for integrated circuits. Background technique [0002] At present, the implementation of digital delay circuits is generally based on the number of input clocks to complete the delay function, without the need for resistors and capacitors, and can be realized through a digital design top-down process. It can be mainly divided into the following three implementation methods: [0003] 1.D flip-flop cascade method, such as figure 1 shown. In this method, N cascaded D flip-flops are included, and the reverse output terminal QN of each stage of D flip-flop is connected to the input terminal D of this stage, and the clock output QN of the D flip-flop is connected to the clock of the next-stage D flip-flop The input terminal CK is connected, and the clock input terminal CK of the first-level D flip-flop is connected to the cl...

AI Technical Summary

Problems solved by technology

This method is a compromise between the above two methods. Although the area of ​​the adder and related combinational logic circuits is reduced, the delay time also has a certain limit, which is n×T period ×2 N , where T period is the input clock period, n is any natural number, N is the number of cascaded D flip-flops, and the counting target is n×2 N , must be even

This method no longer works when the count target is odd

Images